Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	40789	1			T7	287		T8	4		T13	2
auto[SpiFlashAddrCfg]	9519	1			T3	6		T7	81		T13	4
auto[SpiFlashAddr3b]	11577	1			T3	10		T4	4		T7	92
auto[SpiFlashAddr4b]	9458	1			T7	80		T13	6		T16	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40967

1

T3

16

T4

4

T7

329

auto[1]

30376

1

T7

211

T16

26

T11

85

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38215

1

T3

11

T4

4

T7

310

auto[1]

33128

1

T3

5

T7

230

T13

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	46858	1			T3	6		T7	326		T8	4
values[1]	1308	1			T7	17		T12	16		T44	4
values[2]	1804	1			T7	13		T11	4		T12	35
values[3]	1902	1			T7	12		T16	2		T12	35
values[4]	1790	1			T7	8		T11	5		T12	40
values[5]	1871	1			T7	12		T13	2		T14	4
values[6]	1841	1			T7	16		T16	2		T11	6
values[7]	1759	1			T4	4		T7	19		T11	2
values[8]	12210	1			T3	10		T7	117		T13	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38127

1

T8

4

T13

14

T14

12

auto[1]

33216

1

T3

16

T4

4

T7

540

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

68568

1

T3

16

T4

4

T7

511

write

2775

1

T7

29

T13

4

T11

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24731

1

T3

10

T4

4

T7

216

valids[0x1]

46612

1

T3

6

T7

324

T8

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	2004	1			T7	20		T16	2		T11	3
internal_process_ops[0x5a]	2012	1			T7	15		T11	2		T12	32
internal_process_ops[0x05]	23534	1			T7	96		T13	2		T11	146
internal_process_ops[0x35]	1973	1			T7	20		T16	2		T11	6
internal_process_ops[0x15]	1862	1			T7	18		T8	4		T11	2
internal_process_ops[0x03]	1424	1			T3	6		T7	3		T11	6
internal_process_ops[0x0b]	1367	1			T7	10		T11	2		T12	27
internal_process_ops[0x3b]	1419	1			T7	7		T16	2		T17	6
internal_process_ops[0x6b]	1400	1			T3	5		T7	6		T13	2
internal_process_ops[0xbb]	1449	1			T3	5		T4	4		T7	11
internal_process_ops[0xeb]	1419	1			T7	6		T16	2		T11	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69960

1

T3

16

T4

4

T7

526

auto[1]

1383

1

T7

14

T11

2

T31

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68807

1

T3

16

T4

4

T7

508

auto[1]

2536

1

T7

32

T11

12

T12

40

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12239

1

T8

4

T13

2

T14

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8128

1

T16

10

T11

52

T31

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2768

1

T14

4

T11

11

T12

85

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2373

1

T16

10

T11

7

T31

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3313

1

T13

2

T11

12

T12

88

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2877

1

T16

4

T11

8

T31

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2674

1

T13

6

T11

9

T12

81

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2361

1

T16

2

T11

17

T31

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T12

3

T28

1

T29

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T12

2

T27

2

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T12

1

T28

2

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

110

1

T31

2

T28

2

T29

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T13

4

T28

2

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

83

1

T12

4

T28

2

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T12

4

T28

2

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T12

3

T28

1

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T11

1

T12

1

T28

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T12

1

T29

1

T36

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

68

1

T12

3

T28

2

T33

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

75

1

T11

1

T12

2

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

101

1

T11

1

T12

4

T37

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

81

1

T11

1

T12

6

T36

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

72

1

T28

3

T30

1

T34

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

81

1

T12

4

T27

2

T28

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12182

1

T7

178

T12

23

T26

41

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7536

1

T7

99

T12

24

T26

27

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1897

1

T3

6

T7

48

T12

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1818

1

T7

31

T12

4

T26

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2449

1

T3

10

T4

4

T7

53

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2243

1

T7

32

T12

8

T26

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2015

1

T7

37

T12

5

T26

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1695

1

T7

33

T12

6

T26

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T7

3

T28

1

T138

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

69

1

T7

1

T28

2

T138

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

69

1

T7

5

T28

1

T144

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

76

1

T7

1

T26

1

T138

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T7

1

T28

3

T138

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T28

3

T65

1

T145

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T7

1

T26

2

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T144

1

T146

2

T145

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T7

2

T28

2

T138

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T7

2

T26

2

T144

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T7

3

T12

2

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T26

1

T138

2

T147

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

86

1

T138

2

T148

5

T149

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

117

1

T7

4

T28

1

T138

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

91

1

T12

2

T28

3

T65

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

84

1

T7

6

T138

2

T148

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5300	1			T14	8		T11	24		T12	144
auto[0]	values[0]	valids[0x1]	18745	1			T8	4		T13	6		T16	12
auto[0]	values[1]	valids[0x1]	658	1			T12	15		T44	4		T27	4
auto[0]	values[2]	valids[0x0]	686	1			T11	2		T12	26		T27	6
auto[0]	values[2]	valids[0x1]	353	1			T11	2		T12	6		T27	4
auto[0]	values[3]	valids[0x0]	701	1			T16	2		T12	27		T41	8
auto[0]	values[3]	valids[0x1]	457	1			T12	6		T27	2		T28	1
auto[0]	values[4]	valids[0x0]	665	1			T11	2		T12	23		T43	6
auto[0]	values[4]	valids[0x1]	393	1			T11	3		T12	14		T32	2
auto[0]	values[5]	valids[0x0]	750	1			T14	4		T12	23		T27	1
auto[0]	values[5]	valids[0x1]	386	1			T13	2		T11	2		T31	2
auto[0]	values[6]	valids[0x0]	723	1			T16	2		T11	3		T31	4
auto[0]	values[6]	valids[0x1]	352	1			T11	3		T12	10		T27	6
auto[0]	values[7]	valids[0x0]	671	1			T11	2		T12	30		T27	2
auto[0]	values[7]	valids[0x1]	349	1			T12	12		T27	4		T28	5
auto[0]	values[8]	valids[0x0]	4359	1			T13	6		T16	8		T11	20
auto[0]	values[8]	valids[0x1]	2579	1			T16	2		T11	14		T12	92
auto[1]	values[0]	valids[0x0]	5058	1			T7	105		T12	19		T26	30
auto[1]	values[0]	valids[0x1]	17755	1			T3	6		T7	221		T12	40
auto[1]	values[1]	valids[0x1]	650	1			T7	17		T12	1		T26	5
auto[1]	values[2]	valids[0x0]	449	1			T7	11		T12	3		T26	2
auto[1]	values[2]	valids[0x1]	316	1			T7	2		T28	3		T138	2
auto[1]	values[3]	valids[0x0]	453	1			T7	7		T12	1		T26	1
auto[1]	values[3]	valids[0x1]	291	1			T7	5		T12	1		T26	1
auto[1]	values[4]	valids[0x0]	441	1			T7	4		T12	2		T26	4
auto[1]	values[4]	valids[0x1]	291	1			T7	4		T12	1		T26	2
auto[1]	values[5]	valids[0x0]	467	1			T7	9		T12	1		T26	1
auto[1]	values[5]	valids[0x1]	268	1			T7	3		T12	3		T28	3
auto[1]	values[6]	valids[0x0]	435	1			T7	8		T12	2		T28	6
auto[1]	values[6]	valids[0x1]	331	1			T7	8		T12	2		T26	3
auto[1]	values[7]	valids[0x0]	443	1			T4	4		T7	10		T12	1
auto[1]	values[7]	valids[0x1]	296	1			T7	9		T28	8		T138	3
auto[1]	values[8]	valids[0x0]	3130	1			T3	10		T7	62		T17	6
auto[1]	values[8]	valids[0x1]	2142	1			T7	55		T12	6		T26	9