Summary for Variable cp_busy_bit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_busy_bit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20003 |
1 |
|
|
T3 |
23 |
|
T4 |
13 |
|
T7 |
197 |
auto[1] |
23846 |
1 |
|
|
T7 |
112 |
|
T11 |
157 |
|
T12 |
97 |
Summary for Variable cp_is_host_read
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_is_host_read
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16924 |
1 |
|
|
T3 |
23 |
|
T4 |
13 |
|
T7 |
175 |
auto[1] |
26925 |
1 |
|
|
T7 |
134 |
|
T8 |
4 |
|
T13 |
2 |
Summary for Variable cp_other_status
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
8 |
0 |
8 |
100.00 |
Automatically Generated Bins for cp_other_status
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0:524287] |
7458 |
1 |
|
|
T3 |
9 |
|
T4 |
2 |
|
T7 |
43 |
auto[524288:1048575] |
5298 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
52 |
auto[1048576:1572863] |
4992 |
1 |
|
|
T7 |
16 |
|
T8 |
1 |
|
T17 |
7 |
auto[1572864:2097151] |
5366 |
1 |
|
|
T3 |
4 |
|
T4 |
2 |
|
T7 |
32 |
auto[2097152:2621439] |
5279 |
1 |
|
|
T4 |
3 |
|
T7 |
54 |
|
T8 |
1 |
auto[2621440:3145727] |
4758 |
1 |
|
|
T4 |
3 |
|
T7 |
30 |
|
T17 |
2 |
auto[3145728:3670015] |
5091 |
1 |
|
|
T3 |
7 |
|
T4 |
2 |
|
T7 |
73 |
auto[3670016:4194303] |
5607 |
1 |
|
|
T3 |
2 |
|
T7 |
9 |
|
T17 |
1 |
Summary for Variable cp_sw_read_while_csb_active
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_sw_read_while_csb_active
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42937 |
1 |
|
|
T3 |
23 |
|
T4 |
13 |
|
T7 |
306 |
auto[1] |
912 |
1 |
|
|
T7 |
3 |
|
T11 |
4 |
|
T12 |
6 |
Summary for Variable cp_wel_bit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_wel_bit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35095 |
1 |
|
|
T3 |
23 |
|
T4 |
13 |
|
T7 |
234 |
auto[1] |
8754 |
1 |
|
|
T7 |
75 |
|
T11 |
112 |
|
T12 |
117 |
Summary for Cross cr_all_except_csb
Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
64 |
0 |
64 |
100.00 |
|
Automatically Generated Cross Bins for cr_all_except_csb
Bins
cp_busy_bit | cp_wel_bit | cp_other_status | cp_is_host_read | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0:524287] |
auto[0] |
2040 |
1 |
|
|
T3 |
9 |
|
T4 |
2 |
|
T7 |
12 |
auto[0] |
auto[0] |
auto[0:524287] |
auto[1] |
785 |
1 |
|
|
T7 |
6 |
|
T13 |
2 |
|
T11 |
1 |
auto[0] |
auto[0] |
auto[524288:1048575] |
auto[0] |
1367 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
21 |
auto[0] |
auto[0] |
auto[524288:1048575] |
auto[1] |
489 |
1 |
|
|
T7 |
7 |
|
T12 |
7 |
|
T27 |
1 |
auto[0] |
auto[0] |
auto[1048576:1572863] |
auto[0] |
1295 |
1 |
|
|
T7 |
10 |
|
T17 |
7 |
|
T12 |
26 |
auto[0] |
auto[0] |
auto[1048576:1572863] |
auto[1] |
482 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T12 |
17 |
auto[0] |
auto[0] |
auto[1572864:2097151] |
auto[0] |
1445 |
1 |
|
|
T3 |
4 |
|
T4 |
2 |
|
T7 |
11 |
auto[0] |
auto[0] |
auto[1572864:2097151] |
auto[1] |
497 |
1 |
|
|
T7 |
2 |
|
T11 |
2 |
|
T12 |
7 |
auto[0] |
auto[0] |
auto[2097152:2621439] |
auto[0] |
1479 |
1 |
|
|
T4 |
3 |
|
T7 |
16 |
|
T8 |
1 |
auto[0] |
auto[0] |
auto[2097152:2621439] |
auto[1] |
555 |
1 |
|
|
T7 |
5 |
|
T11 |
1 |
|
T12 |
4 |
auto[0] |
auto[0] |
auto[2621440:3145727] |
auto[0] |
1312 |
1 |
|
|
T4 |
3 |
|
T7 |
12 |
|
T17 |
2 |
auto[0] |
auto[0] |
auto[2621440:3145727] |
auto[1] |
510 |
1 |
|
|
T7 |
5 |
|
T12 |
11 |
|
T27 |
3 |
auto[0] |
auto[0] |
auto[3145728:3670015] |
auto[0] |
1410 |
1 |
|
|
T3 |
7 |
|
T4 |
2 |
|
T7 |
25 |
auto[0] |
auto[0] |
auto[3145728:3670015] |
auto[1] |
524 |
1 |
|
|
T7 |
9 |
|
T8 |
3 |
|
T12 |
8 |
auto[0] |
auto[0] |
auto[3670016:4194303] |
auto[0] |
1372 |
1 |
|
|
T3 |
2 |
|
T7 |
4 |
|
T17 |
1 |
auto[0] |
auto[0] |
auto[3670016:4194303] |
auto[1] |
524 |
1 |
|
|
T7 |
1 |
|
T12 |
13 |
|
T44 |
1 |
auto[0] |
auto[1] |
auto[0:524287] |
auto[0] |
373 |
1 |
|
|
T7 |
2 |
|
T11 |
9 |
|
T12 |
6 |
auto[0] |
auto[1] |
auto[0:524287] |
auto[1] |
165 |
1 |
|
|
T7 |
2 |
|
T11 |
4 |
|
T12 |
3 |
auto[0] |
auto[1] |
auto[524288:1048575] |
auto[0] |
355 |
1 |
|
|
T7 |
8 |
|
T11 |
3 |
|
T12 |
1 |
auto[0] |
auto[1] |
auto[524288:1048575] |
auto[1] |
175 |
1 |
|
|
T7 |
6 |
|
T30 |
3 |
|
T138 |
1 |
auto[0] |
auto[1] |
auto[1048576:1572863] |
auto[0] |
328 |
1 |
|
|
T7 |
2 |
|
T12 |
9 |
|
T27 |
1 |
auto[0] |
auto[1] |
auto[1048576:1572863] |
auto[1] |
139 |
1 |
|
|
T7 |
1 |
|
T12 |
4 |
|
T28 |
3 |
auto[0] |
auto[1] |
auto[1572864:2097151] |
auto[0] |
292 |
1 |
|
|
T7 |
5 |
|
T11 |
2 |
|
T12 |
9 |
auto[0] |
auto[1] |
auto[1572864:2097151] |
auto[1] |
164 |
1 |
|
|
T7 |
3 |
|
T11 |
1 |
|
T12 |
8 |
auto[0] |
auto[1] |
auto[2097152:2621439] |
auto[0] |
303 |
1 |
|
|
T7 |
6 |
|
T12 |
4 |
|
T30 |
1 |
auto[0] |
auto[1] |
auto[2097152:2621439] |
auto[1] |
158 |
1 |
|
|
T7 |
3 |
|
T12 |
5 |
|
T138 |
4 |
auto[0] |
auto[1] |
auto[2621440:3145727] |
auto[0] |
336 |
1 |
|
|
T7 |
3 |
|
T12 |
2 |
|
T28 |
3 |
auto[0] |
auto[1] |
auto[2621440:3145727] |
auto[1] |
161 |
1 |
|
|
T7 |
3 |
|
T28 |
1 |
|
T33 |
2 |
auto[0] |
auto[1] |
auto[3145728:3670015] |
auto[0] |
335 |
1 |
|
|
T7 |
4 |
|
T11 |
2 |
|
T12 |
13 |
auto[0] |
auto[1] |
auto[3145728:3670015] |
auto[1] |
117 |
1 |
|
|
T12 |
4 |
|
T28 |
1 |
|
T168 |
1 |
auto[0] |
auto[1] |
auto[3670016:4194303] |
auto[0] |
346 |
1 |
|
|
T7 |
2 |
|
T12 |
14 |
|
T27 |
1 |
auto[0] |
auto[1] |
auto[3670016:4194303] |
auto[1] |
170 |
1 |
|
|
T12 |
7 |
|
T27 |
1 |
|
T28 |
4 |
auto[1] |
auto[0] |
auto[0:524287] |
auto[0] |
331 |
1 |
|
|
T7 |
5 |
|
T11 |
2 |
|
T12 |
3 |
auto[1] |
auto[0] |
auto[0:524287] |
auto[1] |
3128 |
1 |
|
|
T7 |
16 |
|
T11 |
12 |
|
T12 |
3 |
auto[1] |
auto[0] |
auto[524288:1048575] |
auto[0] |
243 |
1 |
|
|
T7 |
3 |
|
T12 |
2 |
|
T26 |
1 |
auto[1] |
auto[0] |
auto[524288:1048575] |
auto[1] |
1973 |
1 |
|
|
T7 |
3 |
|
T12 |
2 |
|
T26 |
2 |
auto[1] |
auto[0] |
auto[1048576:1572863] |
auto[0] |
234 |
1 |
|
|
T7 |
1 |
|
T12 |
7 |
|
T26 |
1 |
auto[1] |
auto[0] |
auto[1048576:1572863] |
auto[1] |
1921 |
1 |
|
|
T7 |
1 |
|
T12 |
11 |
|
T26 |
1 |
auto[1] |
auto[0] |
auto[1572864:2097151] |
auto[0] |
241 |
1 |
|
|
T7 |
2 |
|
T11 |
1 |
|
T12 |
4 |
auto[1] |
auto[0] |
auto[1572864:2097151] |
auto[1] |
2124 |
1 |
|
|
T7 |
5 |
|
T11 |
32 |
|
T12 |
7 |
auto[1] |
auto[0] |
auto[2097152:2621439] |
auto[0] |
280 |
1 |
|
|
T7 |
4 |
|
T11 |
4 |
|
T12 |
1 |
auto[1] |
auto[0] |
auto[2097152:2621439] |
auto[1] |
2110 |
1 |
|
|
T7 |
14 |
|
T11 |
15 |
|
T12 |
1 |
auto[1] |
auto[0] |
auto[2621440:3145727] |
auto[0] |
250 |
1 |
|
|
T7 |
2 |
|
T12 |
4 |
|
T28 |
2 |
auto[1] |
auto[0] |
auto[2621440:3145727] |
auto[1] |
1672 |
1 |
|
|
T7 |
3 |
|
T12 |
5 |
|
T28 |
26 |
auto[1] |
auto[0] |
auto[3145728:3670015] |
auto[0] |
230 |
1 |
|
|
T7 |
7 |
|
T12 |
3 |
|
T27 |
1 |
auto[1] |
auto[0] |
auto[3145728:3670015] |
auto[1] |
1853 |
1 |
|
|
T7 |
21 |
|
T12 |
3 |
|
T27 |
2 |
auto[1] |
auto[0] |
auto[3670016:4194303] |
auto[0] |
239 |
1 |
|
|
T12 |
4 |
|
T27 |
1 |
|
T28 |
5 |
auto[1] |
auto[0] |
auto[3670016:4194303] |
auto[1] |
2180 |
1 |
|
|
T12 |
9 |
|
T27 |
1 |
|
T28 |
73 |
auto[1] |
auto[1] |
auto[0:524287] |
auto[0] |
66 |
1 |
|
|
T11 |
4 |
|
T138 |
1 |
|
T65 |
2 |
auto[1] |
auto[1] |
auto[0:524287] |
auto[1] |
570 |
1 |
|
|
T11 |
69 |
|
T138 |
2 |
|
T65 |
4 |
auto[1] |
auto[1] |
auto[524288:1048575] |
auto[0] |
64 |
1 |
|
|
T7 |
1 |
|
T12 |
1 |
|
T30 |
1 |
auto[1] |
auto[1] |
auto[524288:1048575] |
auto[1] |
632 |
1 |
|
|
T7 |
3 |
|
T12 |
1 |
|
T30 |
43 |
auto[1] |
auto[1] |
auto[1048576:1572863] |
auto[0] |
68 |
1 |
|
|
T12 |
2 |
|
T27 |
1 |
|
T28 |
1 |
auto[1] |
auto[1] |
auto[1048576:1572863] |
auto[1] |
525 |
1 |
|
|
T12 |
3 |
|
T27 |
2 |
|
T28 |
3 |
auto[1] |
auto[1] |
auto[1572864:2097151] |
auto[0] |
57 |
1 |
|
|
T7 |
2 |
|
T12 |
3 |
|
T28 |
1 |
auto[1] |
auto[1] |
auto[1572864:2097151] |
auto[1] |
546 |
1 |
|
|
T7 |
2 |
|
T12 |
4 |
|
T28 |
7 |
auto[1] |
auto[1] |
auto[2097152:2621439] |
auto[0] |
47 |
1 |
|
|
T7 |
1 |
|
T12 |
1 |
|
T33 |
1 |
auto[1] |
auto[1] |
auto[2097152:2621439] |
auto[1] |
347 |
1 |
|
|
T7 |
5 |
|
T12 |
2 |
|
T33 |
56 |
auto[1] |
auto[1] |
auto[2621440:3145727] |
auto[0] |
60 |
1 |
|
|
T7 |
1 |
|
T28 |
2 |
|
T33 |
1 |
auto[1] |
auto[1] |
auto[2621440:3145727] |
auto[1] |
457 |
1 |
|
|
T7 |
1 |
|
T28 |
2 |
|
T33 |
30 |
auto[1] |
auto[1] |
auto[3145728:3670015] |
auto[0] |
54 |
1 |
|
|
T7 |
2 |
|
T11 |
1 |
|
T12 |
3 |
auto[1] |
auto[1] |
auto[3145728:3670015] |
auto[1] |
568 |
1 |
|
|
T7 |
5 |
|
T11 |
17 |
|
T12 |
4 |
auto[1] |
auto[1] |
auto[3670016:4194303] |
auto[0] |
72 |
1 |
|
|
T7 |
1 |
|
T12 |
2 |
|
T138 |
1 |
auto[1] |
auto[1] |
auto[3670016:4194303] |
auto[1] |
704 |
1 |
|
|
T7 |
1 |
|
T12 |
2 |
|
T138 |
77 |
Summary for Cross cr_busyXwelXcsb
Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cr_busyXwelXcsb
Bins
cp_busy_bit | cp_wel_bit | cp_sw_read_while_csb_active | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
15726 |
1 |
|
|
T3 |
23 |
|
T4 |
13 |
|
T7 |
146 |
auto[0] |
auto[0] |
auto[1] |
360 |
1 |
|
|
T7 |
1 |
|
T12 |
2 |
|
T28 |
5 |
auto[0] |
auto[1] |
auto[0] |
3822 |
1 |
|
|
T7 |
50 |
|
T11 |
17 |
|
T12 |
89 |
auto[0] |
auto[1] |
auto[1] |
95 |
1 |
|
|
T11 |
4 |
|
T30 |
1 |
|
T33 |
1 |
auto[1] |
auto[0] |
auto[0] |
18648 |
1 |
|
|
T7 |
85 |
|
T11 |
66 |
|
T12 |
67 |
auto[1] |
auto[0] |
auto[1] |
361 |
1 |
|
|
T7 |
2 |
|
T12 |
2 |
|
T28 |
2 |
auto[1] |
auto[1] |
auto[0] |
4741 |
1 |
|
|
T7 |
25 |
|
T11 |
91 |
|
T12 |
26 |
auto[1] |
auto[1] |
auto[1] |
96 |
1 |
|
|
T12 |
2 |
|
T29 |
1 |
|
T115 |
1 |