Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T8

4

T13

14

T14

12

auto[1]

16404

1

T16

26

T11

85

T31

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3975	1			T11	23		T12	80		T28	75
values[1]	4709	1			T12	170		T43	14		T27	20
values[2]	4201	1			T13	14		T12	81		T32	6
values[3]	3705	1			T14	12		T11	45		T31	16
values[4]	4683	1			T12	90		T38	2		T27	40
values[5]	6556	1			T11	120		T12	123		T41	20
values[6]	5063	1			T8	4		T16	26		T11	57
values[7]	5235	1			T12	139		T37	28		T42	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4296	1			T11	37		T43	14		T27	20
values[1]	4641	1			T11	20		T12	108		T27	20
values[2]	5548	1			T14	12		T11	23		T12	165
values[3]	4471	1			T12	130		T41	20		T27	23
values[4]	4487	1			T11	120		T12	42		T27	20
values[5]	5180	1			T8	4		T11	45		T12	111
values[6]	4760	1			T31	16		T12	125		T32	6
values[7]	4744	1			T13	14		T16	26		T12	167

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	184	1			T28	9		T195	9		T196	8
auto[0]	values[0]	values[1]	151	1			T197	4		T167	30		T198	14
auto[0]	values[0]	values[2]	294	1			T11	11		T12	21		T162	21
auto[0]	values[0]	values[3]	239	1			T114	8		T115	11		T199	18
auto[0]	values[0]	values[4]	349	1			T28	9		T34	12		T65	13
auto[0]	values[0]	values[5]	419	1			T28	10		T50	16		T118	13
auto[0]	values[0]	values[6]	321	1			T12	13		T36	18		T50	12
auto[0]	values[0]	values[7]	267	1			T12	10		T200	2		T115	10
auto[0]	values[1]	values[0]	363	1			T43	14		T27	12		T28	4
auto[0]	values[1]	values[1]	392	1			T12	27		T33	11		T34	12
auto[0]	values[1]	values[2]	460	1			T36	12		T50	16		T65	18
auto[0]	values[1]	values[3]	210	1			T12	7		T34	3		T115	10
auto[0]	values[1]	values[4]	247	1			T135	6		T163	12		T65	16
auto[0]	values[1]	values[5]	467	1			T12	23		T33	14		T170	22
auto[0]	values[1]	values[6]	342	1			T36	10		T162	16		T201	4
auto[0]	values[1]	values[7]	326	1			T12	37		T168	12		T195	7
auto[0]	values[2]	values[0]	307	1			T65	14		T167	58		T64	15
auto[0]	values[2]	values[1]	281	1			T27	9		T162	16		T202	24
auto[0]	values[2]	values[2]	252	1			T12	25		T33	13		T115	12
auto[0]	values[2]	values[3]	488	1			T12	10		T29	39		T34	16
auto[0]	values[2]	values[4]	234	1			T65	17		T203	26		T191	14
auto[0]	values[2]	values[5]	392	1			T12	19		T137	2		T162	16
auto[0]	values[2]	values[6]	386	1			T28	11		T29	9		T204	4
auto[0]	values[2]	values[7]	274	1			T13	14		T36	10		T163	12
auto[0]	values[3]	values[0]	179	1			T34	9		T205	34		T118	11
auto[0]	values[3]	values[1]	229	1			T33	47		T64	23		T206	4
auto[0]	values[3]	values[2]	401	1			T14	12		T12	10		T27	12
auto[0]	values[3]	values[3]	232	1			T12	12		T207	4		T33	14
auto[0]	values[3]	values[4]	210	1			T12	12		T27	5		T29	19
auto[0]	values[3]	values[5]	301	1			T11	11		T208	28		T166	16
auto[0]	values[3]	values[6]	329	1			T44	30		T186	10		T30	13
auto[0]	values[3]	values[7]	206	1			T29	12		T34	12		T162	13
auto[0]	values[4]	values[0]	411	1			T28	22		T33	11		T209	18
auto[0]	values[4]	values[1]	244	1			T30	7		T195	12		T210	13
auto[0]	values[4]	values[2]	439	1			T12	13		T27	9		T28	10
auto[0]	values[4]	values[3]	367	1			T29	33		T211	18		T168	13
auto[0]	values[4]	values[4]	332	1			T212	2		T181	13		T213	59
auto[0]	values[4]	values[5]	258	1			T12	21		T38	2		T27	11
auto[0]	values[4]	values[6]	258	1			T12	26		T64	12		T181	41
auto[0]	values[4]	values[7]	244	1			T50	13		T214	2		T215	6
auto[0]	values[5]	values[0]	257	1			T29	14		T33	49		T65	10
auto[0]	values[5]	values[1]	472	1			T12	10		T28	13		T36	14
auto[0]	values[5]	values[2]	675	1			T12	11		T29	40		T168	147
auto[0]	values[5]	values[3]	306	1			T12	10		T41	20		T216	20
auto[0]	values[5]	values[4]	593	1			T11	114		T12	15		T29	8
auto[0]	values[5]	values[5]	521	1			T217	28		T140	18		T65	69
auto[0]	values[5]	values[6]	330	1			T29	8		T218	12		T65	20
auto[0]	values[5]	values[7]	498	1			T12	22		T35	20		T115	10
auto[0]	values[6]	values[0]	480	1			T11	10		T30	56		T34	15
auto[0]	values[6]	values[1]	462	1			T11	14		T175	18		T50	10
auto[0]	values[6]	values[2]	248	1			T27	22		T33	11		T50	7
auto[0]	values[6]	values[3]	215	1			T29	31		T65	16		T219	22
auto[0]	values[6]	values[4]	288	1			T33	14		T34	14		T50	8
auto[0]	values[6]	values[5]	259	1			T8	4		T12	15		T33	14
auto[0]	values[6]	values[6]	355	1			T12	24		T34	12		T50	28
auto[0]	values[6]	values[7]	584	1			T12	21		T220	4		T28	10
auto[0]	values[7]	values[0]	327	1			T29	15		T36	11		T168	10
auto[0]	values[7]	values[1]	307	1			T12	25		T28	9		T221	12
auto[0]	values[7]	values[2]	441	1			T12	8		T34	23		T141	15
auto[0]	values[7]	values[3]	357	1			T12	18		T27	6		T29	6
auto[0]	values[7]	values[4]	372	1			T50	12		T64	38		T195	10
auto[0]	values[7]	values[5]	437	1			T33	10		T168	10		T115	6
auto[0]	values[7]	values[6]	279	1			T12	12		T50	57		T65	19
auto[0]	values[7]	values[7]	375	1			T37	28		T28	10		T134	8
auto[1]	values[0]	values[0]	135	1			T28	13		T195	11		T222	10
auto[1]	values[0]	values[1]	257	1			T223	24		T167	68		T198	8
auto[1]	values[0]	values[2]	280	1			T11	12		T12	19		T162	9
auto[1]	values[0]	values[3]	232	1			T114	17		T115	9		T224	14
auto[1]	values[0]	values[4]	176	1			T28	19		T34	17		T65	12
auto[1]	values[0]	values[5]	181	1			T28	15		T50	4		T118	7
auto[1]	values[0]	values[6]	319	1			T12	7		T36	6		T50	8
auto[1]	values[0]	values[7]	171	1			T12	10		T115	13		T162	33
auto[1]	values[1]	values[0]	237	1			T27	8		T28	16		T180	28
auto[1]	values[1]	values[1]	231	1			T12	15		T33	51		T34	8
auto[1]	values[1]	values[2]	202	1			T36	51		T50	4		T65	2
auto[1]	values[1]	values[3]	269	1			T12	13		T34	20		T225	10
auto[1]	values[1]	values[4]	190	1			T163	8		T65	7		T210	13
auto[1]	values[1]	values[5]	273	1			T12	21		T33	8		T162	11
auto[1]	values[1]	values[6]	193	1			T36	10		T162	4		T210	10
auto[1]	values[1]	values[7]	307	1			T12	27		T168	71		T195	13
auto[1]	values[2]	values[0]	128	1			T65	8		T167	3		T64	5
auto[1]	values[2]	values[1]	180	1			T27	11		T162	9		T189	14
auto[1]	values[2]	values[2]	254	1			T12	15		T33	63		T115	8
auto[1]	values[2]	values[3]	264	1			T12	10		T29	9		T34	6
auto[1]	values[2]	values[4]	118	1			T65	5		T191	6		T224	8
auto[1]	values[2]	values[5]	154	1			T12	2		T162	10		T184	18
auto[1]	values[2]	values[6]	260	1			T32	6		T28	11		T29	39
auto[1]	values[2]	values[7]	229	1			T36	10		T163	8		T114	16
auto[1]	values[3]	values[0]	117	1			T34	12		T226	10		T118	16
auto[1]	values[3]	values[1]	354	1			T33	4		T64	9		T227	22
auto[1]	values[3]	values[2]	229	1			T12	10		T27	11		T28	19
auto[1]	values[3]	values[3]	226	1			T12	10		T33	8		T50	12
auto[1]	values[3]	values[4]	188	1			T12	8		T27	15		T29	33
auto[1]	values[3]	values[5]	212	1			T11	34		T228	20		T166	8
auto[1]	values[3]	values[6]	127	1			T31	16		T30	7		T115	7
auto[1]	values[3]	values[7]	165	1			T29	8		T34	13		T162	8
auto[1]	values[4]	values[0]	372	1			T28	6		T33	9		T64	9
auto[1]	values[4]	values[1]	359	1			T30	13		T195	82		T210	9
auto[1]	values[4]	values[2]	244	1			T12	9		T27	11		T28	10
auto[1]	values[4]	values[3]	257	1			T29	9		T168	23		T64	9
auto[1]	values[4]	values[4]	243	1			T181	102		T213	8		T174	6
auto[1]	values[4]	values[5]	118	1			T12	5		T27	9		T28	18
auto[1]	values[4]	values[6]	250	1			T12	16		T64	44		T181	9
auto[1]	values[4]	values[7]	287	1			T50	7		T167	12		T184	11
auto[1]	values[5]	values[0]	265	1			T29	6		T33	4		T65	10
auto[1]	values[5]	values[1]	314	1			T12	10		T28	10		T36	6
auto[1]	values[5]	values[2]	628	1			T12	9		T29	6		T168	49
auto[1]	values[5]	values[3]	194	1			T12	10		T192	7		T229	12
auto[1]	values[5]	values[4]	344	1			T11	6		T12	7		T29	12
auto[1]	values[5]	values[5]	410	1			T65	31		T162	23		T230	10
auto[1]	values[5]	values[6]	443	1			T29	35		T65	11		T162	11
auto[1]	values[5]	values[7]	306	1			T12	19		T115	12		T162	4
auto[1]	values[6]	values[0]	295	1			T11	27		T30	7		T34	7
auto[1]	values[6]	values[1]	229	1			T11	6		T50	10		T114	7
auto[1]	values[6]	values[2]	300	1			T27	19		T33	9		T50	13
auto[1]	values[6]	values[3]	158	1			T29	5		T65	9		T231	12
auto[1]	values[6]	values[4]	377	1			T33	6		T34	9		T50	34
auto[1]	values[6]	values[5]	329	1			T12	5		T33	62		T115	5
auto[1]	values[6]	values[6]	277	1			T12	17		T34	8		T50	20
auto[1]	values[6]	values[7]	207	1			T16	26		T12	21		T28	11
auto[1]	values[7]	values[0]	239	1			T29	5		T36	9		T168	10
auto[1]	values[7]	values[1]	179	1			T12	21		T28	13		T181	7
auto[1]	values[7]	values[2]	201	1			T12	15		T34	19		T141	8
auto[1]	values[7]	values[3]	457	1			T12	30		T27	17		T29	27
auto[1]	values[7]	values[4]	226	1			T50	10		T64	14		T195	10
auto[1]	values[7]	values[5]	449	1			T33	10		T168	10		T115	15
auto[1]	values[7]	values[6]	291	1			T12	10		T42	24		T50	6
auto[1]	values[7]	values[7]	298	1			T28	11		T34	16		T168	10