Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	574	1			T11	4		T12	16		T27	1
auto[ReadAddrCrossIntoMailbox]	401	1			T12	14		T27	2		T28	1
auto[ReadAddrCrossOutOfMailbox]	434	1			T11	5		T12	16		T27	7
auto[ReadAddrCrossAllMailbox]	269	1			T11	1		T12	7		T27	1
auto[ReadAddrOutsideMailbox]	4524	1			T13	2		T16	12		T11	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3090

1

T13

1

T16

6

T11

12

auto[1]

3112

1

T13

1

T16

6

T11

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1075	1			T11	6		T12	25		T27	10
read_ops[0x0b]	991	1			T11	2		T12	26		T37	6
read_ops[0x3b]	1064	1			T16	2		T11	2		T12	39
read_ops[0x6b]	991	1			T13	2		T16	8		T11	7
read_ops[0xbb]	1077	1			T11	2		T31	4		T12	26
read_ops[0xeb]	1004	1			T16	2		T11	3		T12	30

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	62	1			T11	2		T30	1		T34	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T12	1		T140	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T12	1		T186	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T12	2		T27	1		T186	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	51	1			T186	2		T30	1		T140	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T12	1		T27	1		T186	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T140	1		T203	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	1		T29	1		T140	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	408	1			T11	1		T12	13		T28	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	383	1			T11	3		T12	6		T27	8
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T12	2		T34	1		T140	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T12	1		T27	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T140	1		T162	1		T64	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T27	1		T29	1		T140	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T12	2		T34	2		T168	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T12	1		T27	1		T167	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T12	1		T163	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T12	1		T65	1		T167	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	345	1			T11	1		T12	7		T37	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	389	1			T11	1		T12	11		T37	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T11	1		T12	4		T29	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	58	1			T12	1		T34	3		T168	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T12	1		T34	2		T168	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T12	2		T168	1		T50	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	46	1			T11	1		T12	5		T27	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T12	1		T29	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T12	1		T29	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T33	1		T34	1		T50	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	405	1			T16	1		T12	10		T41	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	365	1			T16	1		T12	14		T41	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T12	1		T171	2		T167	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T29	1		T163	2		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T12	2		T114	1		T115	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T12	3		T168	2		T50	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T11	1		T29	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T11	1		T27	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T12	2		T33	1		T115	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T12	1		T168	2		T118	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	372	1			T13	1		T16	4		T11	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	346	1			T13	1		T16	4		T11	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T30	1		T115	1		T188	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	60	1			T12	4		T34	2		T168	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T28	1		T36	1		T140	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T140	1		T50	1		T65	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T11	2		T12	2		T29	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T12	1		T27	1		T34	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T140	1		T232	1		T162	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T140	1		T232	1		T167	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	376	1			T31	2		T12	10		T41	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	431	1			T31	2		T12	9		T41	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	52	1			T12	2		T29	1		T175	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T11	1		T36	1		T175	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T12	2		T33	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T12	1		T34	1		T114	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	43	1			T12	1		T27	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T12	2		T168	1		T65	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T50	1		T118	1		T162	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T11	1		T27	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	342	1			T16	1		T12	7		T41	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	362	1			T16	1		T11	1		T12	15