Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	8524853	1			T3	3168		T4	3905		T6	24
all_pins[1]	8524853	1			T3	3168		T4	3905		T6	24
all_pins[2]	8524853	1			T3	3168		T4	3905		T6	24
all_pins[3]	8524853	1			T3	3168		T4	3905		T6	24
all_pins[4]	8524853	1			T3	3168		T4	3905		T6	24
all_pins[5]	8524853	1			T3	3168		T4	3905		T6	24

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51138105	1			T3	19008		T4	23430		T6	144
values[0x1]	11013	1			T48	7		T49	31		T50	24
transitions[0x0=>0x1]	9385	1			T48	7		T49	26		T50	21
transitions[0x1=>0x0]	9410	1			T48	7		T49	26		T50	21

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	8522464	1			T3	3168		T4	3905		T6	24
all_pins[0]	values[0x1]	2389	1			T48	1		T49	3		T50	5
all_pins[0]	transitions[0x0=>0x1]	1669	1			T48	1		T49	2		T50	2
all_pins[0]	transitions[0x1=>0x0]	275	1			T49	6		T50	3		T143	1
all_pins[1]	values[0x0]	8523858	1			T3	3168		T4	3905		T6	24
all_pins[1]	values[0x1]	995	1			T49	7		T50	6		T51	2
all_pins[1]	transitions[0x0=>0x1]	672	1			T49	6		T50	6		T51	1
all_pins[1]	transitions[0x1=>0x0]	207	1			T48	2		T49	4		T50	2
all_pins[2]	values[0x0]	8524323	1			T3	3168		T4	3905		T6	24
all_pins[2]	values[0x1]	530	1			T48	2		T49	5		T50	2
all_pins[2]	transitions[0x0=>0x1]	481	1			T48	2		T49	3		T50	2
all_pins[2]	transitions[0x1=>0x0]	140	1			T48	1		T49	4		T50	1
all_pins[3]	values[0x0]	8524664	1			T3	3168		T4	3905		T6	24
all_pins[3]	values[0x1]	189	1			T48	1		T49	6		T50	1
all_pins[3]	transitions[0x0=>0x1]	136	1			T48	1		T49	5		T50	1
all_pins[3]	transitions[0x1=>0x0]	145	1			T48	2		T49	7		T50	5
all_pins[4]	values[0x0]	8524655	1			T3	3168		T4	3905		T6	24
all_pins[4]	values[0x1]	198	1			T48	2		T49	8		T50	5
all_pins[4]	transitions[0x0=>0x1]	152	1			T48	2		T49	8		T50	5
all_pins[4]	transitions[0x1=>0x0]	6666	1			T48	1		T49	2		T50	5
all_pins[5]	values[0x0]	8518141	1			T3	3168		T4	3905		T6	24
all_pins[5]	values[0x1]	6712	1			T48	1		T49	2		T50	5
all_pins[5]	transitions[0x0=>0x1]	6275	1			T48	1		T49	2		T50	5
all_pins[5]	transitions[0x1=>0x0]	1977	1			T48	1		T49	3		T50	5