Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4894	1			T11	20		T12	153		T38	2
values[1]	4138	1			T11	23		T12	88		T27	20
values[2]	4182	1			T11	37		T12	126		T27	63
values[3]	5431	1			T16	26		T11	165		T31	16
values[4]	4209	1			T12	61		T27	20		T28	44
values[5]	5255	1			T8	4		T13	14		T14	12
values[6]	4665	1			T12	80		T32	6		T42	24
values[7]	5353	1			T12	129		T44	30		T35	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4931	1			T14	12		T12	42		T38	2
values[1]	4392	1			T12	86		T32	6		T42	24
values[2]	4683	1			T16	26		T11	65		T12	120
values[3]	4642	1			T11	120		T31	16		T12	89
values[4]	5583	1			T8	4		T11	37		T12	126
values[5]	5272	1			T12	108		T43	14		T27	61
values[6]	4303	1			T12	128		T44	30		T27	20
values[7]	4321	1			T13	14		T11	23		T12	149

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37435

1

T8

4

T13

14

T14

12

auto[1]

692

1

T11

2

T31

2

T12

22

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	614	1			T12	22		T38	2		T233	36
auto[0]	values[0]	values[1]	591	1			T12	22		T27	21		T29	28
auto[0]	values[0]	values[2]	604	1			T11	20		T12	19		T29	45
auto[0]	values[0]	values[3]	606	1			T29	40		T115	23		T65	22
auto[0]	values[0]	values[4]	670	1			T34	28		T139	8		T208	28
auto[0]	values[0]	values[5]	750	1			T27	20		T36	60		T34	19
auto[0]	values[0]	values[6]	420	1			T12	46		T207	4		T50	20
auto[0]	values[0]	values[7]	532	1			T12	42		T28	28		T29	47
auto[0]	values[1]	values[0]	683	1			T28	35		T168	146		T50	22
auto[0]	values[1]	values[1]	516	1			T29	23		T205	34		T65	25
auto[0]	values[1]	values[2]	471	1			T115	20		T162	23		T64	20
auto[0]	values[1]	values[3]	447	1			T12	22		T28	22		T163	20
auto[0]	values[1]	values[4]	366	1			T12	20		T65	20		T162	20
auto[0]	values[1]	values[5]	531	1			T27	20		T29	30		T209	18
auto[0]	values[1]	values[6]	416	1			T28	20		T115	39		T65	22
auto[0]	values[1]	values[7]	637	1			T11	22		T12	43		T190	20
auto[0]	values[2]	values[0]	602	1			T12	20		T27	20		T65	26
auto[0]	values[2]	values[1]	438	1			T12	22		T134	8		T114	27
auto[0]	values[2]	values[2]	589	1			T12	20		T27	20		T204	4
auto[0]	values[2]	values[3]	347	1			T50	20		T160	31		T234	16
auto[0]	values[2]	values[4]	759	1			T11	37		T12	21		T27	23
auto[0]	values[2]	values[5]	391	1			T12	21		T33	22		T50	20
auto[0]	values[2]	values[6]	581	1			T34	20		T235	18		T198	17
auto[0]	values[2]	values[7]	403	1			T12	20		T236	24		T34	22
auto[0]	values[3]	values[0]	606	1			T41	20		T33	20		T36	24
auto[0]	values[3]	values[1]	652	1			T12	20		T30	81		T163	20
auto[0]	values[3]	values[2]	653	1			T16	26		T11	45		T12	20
auto[0]	values[3]	values[3]	853	1			T11	119		T31	14		T12	21
auto[0]	values[3]	values[4]	634	1			T29	20		T34	22		T226	10
auto[0]	values[3]	values[5]	454	1			T29	36		T36	18		T34	16
auto[0]	values[3]	values[6]	676	1			T12	19		T28	20		T29	22
auto[0]	values[3]	values[7]	799	1			T37	28		T28	20		T34	20
auto[0]	values[4]	values[0]	458	1			T180	28		T167	20		T237	6
auto[0]	values[4]	values[1]	554	1			T238	2		T193	2		T223	24
auto[0]	values[4]	values[2]	522	1			T211	18		T34	23		T65	35
auto[0]	values[4]	values[3]	446	1			T12	20		T28	20		T239	4
auto[0]	values[4]	values[4]	672	1			T163	22		T169	26		T162	20
auto[0]	values[4]	values[5]	475	1			T12	20		T33	49		T50	20
auto[0]	values[4]	values[6]	423	1			T12	18		T27	20		T115	20
auto[0]	values[4]	values[7]	586	1			T28	23		T50	40		T162	20
auto[0]	values[5]	values[0]	575	1			T14	12		T36	18		T65	25
auto[0]	values[5]	values[1]	712	1			T12	21		T33	76		T141	21
auto[0]	values[5]	values[2]	494	1			T12	19		T28	19		T50	23
auto[0]	values[5]	values[3]	665	1			T12	24		T168	40		T65	31
auto[0]	values[5]	values[4]	660	1			T8	4		T12	42		T162	112
auto[0]	values[5]	values[5]	1207	1			T43	14		T27	21		T28	21
auto[0]	values[5]	values[6]	447	1			T186	10		T29	20		T34	44
auto[0]	values[5]	values[7]	389	1			T13	14		T12	20		T36	20
auto[0]	values[6]	values[0]	669	1			T220	4		T28	23		T217	28
auto[0]	values[6]	values[1]	506	1			T32	4		T42	24		T137	2
auto[0]	values[6]	values[2]	577	1			T12	20		T167	20		T64	20
auto[0]	values[6]	values[3]	593	1			T36	40		T240	10		T160	20
auto[0]	values[6]	values[4]	754	1			T12	20		T28	25		T33	20
auto[0]	values[6]	values[5]	637	1			T12	19		T33	83		T34	19
auto[0]	values[6]	values[6]	484	1			T12	20		T232	18		T241	4
auto[0]	values[6]	values[7]	374	1			T168	20		T114	27		T115	20
auto[0]	values[7]	values[0]	667	1			T28	20		T33	20		T167	20
auto[0]	values[7]	values[1]	345	1			T35	20		T29	19		T162	44
auto[0]	values[7]	values[2]	668	1			T12	18		T50	80		T65	19
auto[0]	values[7]	values[3]	598	1			T28	25		T242	12		T50	20
auto[0]	values[7]	values[4]	961	1			T12	21		T163	20		T50	18
auto[0]	values[7]	values[5]	726	1			T12	44		T141	22		T198	20
auto[0]	values[7]	values[6]	768	1			T12	19		T44	30		T65	22
auto[0]	values[7]	values[7]	532	1			T12	21		T30	19		T114	24
auto[1]	values[0]	values[0]	10	1			T65	3		T61	2		T184	1
auto[1]	values[0]	values[1]	15	1			T27	2		T64	6		T187	1
auto[1]	values[0]	values[2]	18	1			T12	1		T29	3		T34	1
auto[1]	values[0]	values[3]	10	1			T29	3		T231	4		T192	1
auto[1]	values[0]	values[4]	16	1			T34	1		T167	2		T61	3
auto[1]	values[0]	values[5]	18	1			T36	3		T34	1		T162	2
auto[1]	values[0]	values[6]	8	1			T12	1		T243	2		T244	3
auto[1]	values[0]	values[7]	12	1			T29	1		T33	2		T167	2
auto[1]	values[1]	values[0]	5	1			T115	1		T64	1		T184	1
auto[1]	values[1]	values[1]	9	1			T29	1		T182	1		T245	3
auto[1]	values[1]	values[2]	7	1			T162	2		T246	1		T247	3
auto[1]	values[1]	values[3]	7	1			T65	1		T166	2		T187	1
auto[1]	values[1]	values[4]	10	1			T187	4		T248	1		T249	3
auto[1]	values[1]	values[5]	10	1			T194	1		T250	2		T251	1
auto[1]	values[1]	values[6]	10	1			T115	1		T65	1		T160	2
auto[1]	values[1]	values[7]	13	1			T11	1		T12	3		T34	1
auto[1]	values[2]	values[0]	9	1			T252	1		T187	1		T253	4
auto[1]	values[2]	values[1]	9	1			T12	1		T114	5		T115	1
auto[1]	values[2]	values[2]	9	1			T65	1		T162	3		T192	3
auto[1]	values[2]	values[3]	4	1			T254	4		-	-		-	-
auto[1]	values[2]	values[4]	14	1			T33	1		T64	4		T192	1
auto[1]	values[2]	values[5]	5	1			T12	1		T255	1		T256	1
auto[1]	values[2]	values[6]	16	1			T34	1		T198	3		T194	1
auto[1]	values[2]	values[7]	6	1			T179	3		T257	1		T258	2
auto[1]	values[3]	values[0]	2	1			T162	1		T194	1		-	-
auto[1]	values[3]	values[1]	12	1			T30	2		T194	2		T182	1
auto[1]	values[3]	values[2]	9	1			T34	1		T64	2		T194	1
auto[1]	values[3]	values[3]	23	1			T11	1		T31	2		T27	2
auto[1]	values[3]	values[4]	16	1			T118	1		T259	2		T260	2
auto[1]	values[3]	values[5]	14	1			T36	2		T34	4		T168	1
auto[1]	values[3]	values[6]	19	1			T12	1		T28	2		T118	1
auto[1]	values[3]	values[7]	9	1			T28	1		T261	1		T262	1
auto[1]	values[4]	values[0]	8	1			T263	1		T264	1		T265	1
auto[1]	values[4]	values[1]	9	1			T160	3		T191	2		T266	1
auto[1]	values[4]	values[2]	12	1			T65	1		T255	1		T261	5
auto[1]	values[4]	values[3]	8	1			T28	1		T194	4		T257	1
auto[1]	values[4]	values[4]	10	1			T167	2		T174	2		T178	1
auto[1]	values[4]	values[5]	5	1			T33	2		T162	1		T184	1
auto[1]	values[4]	values[6]	13	1			T12	3		T64	1		T166	1
auto[1]	values[4]	values[7]	8	1			T50	2		T191	1		T248	2
auto[1]	values[5]	values[0]	9	1			T36	2		T64	2		T166	3
auto[1]	values[5]	values[1]	9	1			T167	4		T181	2		T192	1
auto[1]	values[5]	values[2]	14	1			T12	1		T28	1		T50	1
auto[1]	values[5]	values[3]	19	1			T12	2		T65	2		T162	3
auto[1]	values[5]	values[4]	17	1			T12	1		T162	4		T224	1
auto[1]	values[5]	values[5]	26	1			T28	1		T168	2		T65	2
auto[1]	values[5]	values[6]	7	1			T34	1		T178	1		T250	2
auto[1]	values[5]	values[7]	5	1			T191	1		T252	2		T224	1
auto[1]	values[6]	values[0]	7	1			T118	1		T64	1		T195	1
auto[1]	values[6]	values[1]	9	1			T32	2		T184	1		T267	1
auto[1]	values[6]	values[2]	8	1			T224	1		T248	1		T260	5
auto[1]	values[6]	values[3]	13	1			T36	2		T244	2		T222	1
auto[1]	values[6]	values[4]	10	1			T28	3		T255	2		T268	1
auto[1]	values[6]	values[5]	12	1			T12	1		T33	2		T34	1
auto[1]	values[6]	values[6]	5	1			T246	1		T269	1		T261	1
auto[1]	values[6]	values[7]	7	1			T114	1		T184	1		T195	1
auto[1]	values[7]	values[0]	7	1			T189	1		T270	1		T179	2
auto[1]	values[7]	values[1]	6	1			T29	1		T244	1		T267	3
auto[1]	values[7]	values[2]	28	1			T12	2		T50	3		T65	1
auto[1]	values[7]	values[3]	3	1			T192	1		T271	2		-	-
auto[1]	values[7]	values[4]	14	1			T12	1		T50	2		T160	2
auto[1]	values[7]	values[5]	11	1			T12	2		T141	1		T194	1
auto[1]	values[7]	values[6]	10	1			T12	1		T65	1		T167	3
auto[1]	values[7]	values[7]	9	1			T30	1		T252	1		T266	1