Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2760

1

T7

21

T10

5

T18

6

auto[1]

2729

1

T7

23

T10

3

T18

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2920

1

T7

35

T18

12

T21

11

auto[1]

2569

1

T7

9

T10

8

T19

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4388

1

T7

31

T10

8

T18

6

auto[1]

1101

1

T7

13

T18

6

T21

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1098	1			T7	11		T10	2		T19	2
valid[1]	1109	1			T7	6		T10	3		T18	2
valid[2]	1111	1			T7	8		T10	1		T18	4
valid[3]	1062	1			T7	10		T10	1		T18	3
valid[4]	1109	1			T7	9		T10	1		T18	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	200	1			T7	4		T21	1		T12	3
auto[0]	auto[0]	valid[0]	auto[1]	256	1			T7	1		T10	2		T19	1
auto[0]	auto[0]	valid[1]	auto[0]	194	1			T7	1		T18	1		T22	2
auto[0]	auto[0]	valid[1]	auto[1]	245	1			T7	1		T10	2		T19	1
auto[0]	auto[0]	valid[2]	auto[0]	177	1			T7	1		T12	2		T27	1
auto[0]	auto[0]	valid[2]	auto[1]	268	1			T7	2		T19	3		T12	2
auto[0]	auto[0]	valid[3]	auto[0]	188	1			T7	3		T21	1		T12	5
auto[0]	auto[0]	valid[3]	auto[1]	234	1			T7	1		T10	1		T19	2
auto[0]	auto[0]	valid[4]	auto[0]	183	1			T18	1		T21	2		T12	6
auto[0]	auto[0]	valid[4]	auto[1]	256	1			T7	1		T12	4		T39	3
auto[0]	auto[1]	valid[0]	auto[0]	177	1			T7	3		T22	1		T11	1
auto[0]	auto[1]	valid[0]	auto[1]	258	1			T19	1		T12	5		T39	2
auto[0]	auto[1]	valid[1]	auto[0]	187	1			T7	1		T21	1		T22	1
auto[0]	auto[1]	valid[1]	auto[1]	265	1			T7	1		T10	1		T19	2
auto[0]	auto[1]	valid[2]	auto[0]	167	1			T7	2		T18	3		T11	1
auto[0]	auto[1]	valid[2]	auto[1]	277	1			T7	1		T10	1		T19	3
auto[0]	auto[1]	valid[3]	auto[0]	165	1			T7	2		T21	1		T22	1
auto[0]	auto[1]	valid[3]	auto[1]	256	1			T7	1		T19	4		T12	2
auto[0]	auto[1]	valid[4]	auto[0]	181	1			T7	5		T18	1		T21	1
auto[0]	auto[1]	valid[4]	auto[1]	254	1			T10	1		T19	3		T12	4
auto[1]	auto[0]	valid[0]	auto[0]	116	1			T7	2		T21	1		T22	1
auto[1]	auto[0]	valid[1]	auto[0]	104	1			T18	1		T12	1		T138	2
auto[1]	auto[0]	valid[2]	auto[0]	112	1			T7	2		T18	1		T12	4
auto[1]	auto[0]	valid[3]	auto[0]	112	1			T7	1		T18	1		T12	5
auto[1]	auto[0]	valid[4]	auto[0]	115	1			T7	1		T18	1		T12	5
auto[1]	auto[1]	valid[0]	auto[0]	91	1			T7	1		T21	1		T22	1
auto[1]	auto[1]	valid[1]	auto[0]	114	1			T7	2		T12	4		T34	1
auto[1]	auto[1]	valid[2]	auto[0]	110	1			T12	1		T28	1		T81	2
auto[1]	auto[1]	valid[3]	auto[0]	107	1			T7	2		T18	2		T21	1
auto[1]	auto[1]	valid[4]	auto[0]	120	1			T7	2		T21	1		T12	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal