Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75432

1

T6

9

T7

941

T18

286

auto[1]

26372

1

T7

97

T10

8

T19

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74307

1

T6

4

T7

721

T10

8

auto[1]

27497

1

T6

5

T7

317

T18

92

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	52318	1			T6	8		T7	554		T10	8
others[1]	8592	1			T7	90		T18	24		T21	16
others[2]	8502	1			T6	1		T7	81		T18	22
others[3]	9749	1			T7	90		T18	32		T21	16
interest[1]	5591	1			T7	57		T18	11		T21	9
interest[4]	34188	1			T6	7		T7	348		T10	8
interest[64]	17052	1			T7	166		T18	44		T21	36

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24526	1			T6	4		T7	341		T18	104
auto[0]	auto[0]	others[1]	4102	1			T7	56		T18	19		T21	10
auto[0]	auto[0]	others[2]	4033	1			T7	49		T18	14		T21	16
auto[0]	auto[0]	others[3]	4590	1			T7	50		T18	21		T21	8
auto[0]	auto[0]	interest[1]	2645	1			T7	37		T18	6		T21	7
auto[0]	auto[0]	interest[4]	15913	1			T6	3		T7	207		T18	71
auto[0]	auto[0]	interest[64]	8039	1			T7	91		T18	30		T21	22
auto[0]	auto[1]	others[0]	13770	1			T7	48		T10	8		T19	20
auto[0]	auto[1]	others[1]	2170	1			T7	9		T12	20		T26	8
auto[0]	auto[1]	others[2]	2135	1			T7	6		T11	2		T12	32
auto[0]	auto[1]	others[3]	2528	1			T7	12		T11	1		T12	27
auto[0]	auto[1]	interest[1]	1439	1			T7	4		T11	1		T12	22
auto[0]	auto[1]	interest[4]	9121	1			T7	35		T10	8		T19	20
auto[0]	auto[1]	interest[64]	4330	1			T7	18		T11	2		T12	65
auto[1]	auto[0]	others[0]	14022	1			T6	4		T7	165		T18	49
auto[1]	auto[0]	others[1]	2320	1			T7	25		T18	5		T21	6
auto[1]	auto[0]	others[2]	2334	1			T6	1		T7	26		T18	8
auto[1]	auto[0]	others[3]	2631	1			T7	28		T18	11		T21	8
auto[1]	auto[0]	interest[1]	1507	1			T7	16		T18	5		T21	2
auto[1]	auto[0]	interest[4]	9154	1			T6	4		T7	106		T18	28
auto[1]	auto[0]	interest[64]	4683	1			T7	57		T18	14		T21	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal