Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	2	34	94.44

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	2	34	94.44	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	798	1			T48	7		T49	24		T50	17
all_values[1]	798	1			T48	7		T49	24		T50	17
all_values[2]	798	1			T48	7		T49	24		T50	17
all_values[3]	798	1			T48	7		T49	24		T50	17
all_values[4]	798	1			T48	7		T49	24		T50	17
all_values[5]	798	1			T48	7		T49	24		T50	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2568

1

T48

23

T49

71

T50

46

auto[1]

2220

1

T48

19

T49

73

T50

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1905

1

T48

17

T49

60

T50

47

auto[1]

2883

1

T48

25

T49

84

T50

55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2708

1

T48

23

T49

85

T50

61

auto[1]

2080

1

T48

19

T49

59

T50

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	2	34	94.44	2
Automatically Generated Cross Bins	36	2	34	94.44	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	155	1			T48	1		T49	6		T50	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T49	4		T50	1		T143	1
all_values[0]	auto[0]	auto[1]	auto[0]	120	1			T48	4		T49	6		T50	4
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T49	2		T50	3		T51	3
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T49	2		T50	5		T51	2
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T48	2		T49	4		T50	2
all_values[1]	auto[0]	auto[0]	auto[0]	166	1			T48	3		T49	2		T50	4
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T49	1		T51	2		T131	1
all_values[1]	auto[0]	auto[1]	auto[0]	153	1			T48	1		T49	9		T50	4
all_values[1]	auto[0]	auto[1]	auto[1]	61	1			T49	2		T50	2		T51	1
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T48	3		T49	3		T50	1
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T49	7		T50	6		T51	3
all_values[2]	auto[0]	auto[0]	auto[0]	160	1			T48	1		T49	3		T50	5
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T48	1		T49	2		T50	2
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T49	6		T50	6		T51	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T48	2		T49	3		T50	1
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T48	2		T49	6		T50	1
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T48	1		T49	4		T50	2
all_values[3]	auto[0]	auto[0]	auto[0]	162	1			T49	1		T50	2		T51	3
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T48	1		T49	4		T50	1
all_values[3]	auto[0]	auto[1]	auto[0]	143	1			T48	3		T49	3		T50	6
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T49	1		T50	1		T143	1
all_values[3]	auto[1]	auto[0]	auto[1]	187	1			T48	2		T49	9		T50	4
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T48	1		T49	6		T50	3
all_values[4]	auto[0]	auto[0]	auto[0]	152	1			T48	1		T49	6		T50	3
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T48	1		T49	2		T50	1
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T49	4		T50	3		T51	2
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T48	1		T49	4		T50	2
all_values[4]	auto[1]	auto[0]	auto[1]	195	1			T48	4		T49	2		T50	5
all_values[4]	auto[1]	auto[1]	auto[1]	147	1			T49	6		T50	3		T51	2
all_values[5]	auto[0]	auto[0]	auto[0]	217	1			T48	1		T49	9		T50	7
all_values[5]	auto[0]	auto[1]	auto[0]	217	1			T48	2		T49	5		T50	1
all_values[5]	auto[1]	auto[0]	auto[1]	197	1			T48	2		T49	9		T50	2
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T48	2		T49	1		T50	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal