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 LINE       19445
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T18,T22,T16

 LINE       19445
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T14
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T14
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T22,T14
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T22,T14
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T11,T32
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T6,T7,T10
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T11,T81
1	1	Covered	T6,T7,T18

 LINE       19445
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T18
1	1	Covered	T18,T22,T16

 LINE       19445
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T7,T10,T18
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T18
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T13
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T21
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T7,T18,T13
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T21
1	1	Covered	T18,T13,T22

 LINE       19445
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T21
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T7,T18,T21
1	1	Covered	T18,T16,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T18
1	1	Covered	T6,T7,T18

 LINE       19445
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T18
1	1	Covered	T18,T22,T11

 LINE       19445
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T6,T7,T18
1	1	Covered	T6,T7,T18

 LINE       19523
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T6

 LINE       19534
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T18,T13,T22
1	1	0	Covered	T74,T77,T82
1	1	1	Covered	T48,T49,T50

 LINE       19547
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T18,T22,T11
1	1	0	Covered	T74,T80,T83
1	1	1	Covered	T48,T49,T50

 LINE       19560
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T6
1	0	1	Covered	T1,T5,T18
1	1	0	Covered	T80,T84,T85
1	1	1	Covered	T1,T5,T46

 LINE       19563
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       19568
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       19579
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T20
1	1	0	Not Covered
1	1	1	Covered	T7,T20,T24

 LINE       19580
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       19589
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T11

 LINE       19590
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T82
1	1	1	Covered	T3,T4,T7

 LINE       19593
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       19594
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       19595
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       19602
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T7,T8
1	1	0	Covered	T74,T77,T82
1	1	1	Covered	T4,T7,T8

 LINE       19607
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       19612
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       19615
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T74,T77,T84
1	1	1	Covered	T3,T4,T7

 LINE       19618
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T13
1	1	0	Not Covered
1	1	1	Covered	T7,T11,T12

 LINE       19619
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T13
1	1	0	Not Covered
1	1	1	Covered	T7,T11,T12

 LINE       19620
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T83
1	1	1	Covered	T3,T4,T7

 LINE       19685
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       19750
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T84
1	1	1	Covered	T3,T4,T7

 LINE       19815
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T85
1	1	1	Covered	T3,T4,T7

 LINE       19880
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       19945
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T84
1	1	1	Covered	T3,T4,T7

 LINE       20010
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       20075
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T85,T83
1	1	1	Covered	T3,T4,T7

 LINE       20140
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T84
1	1	1	Covered	T3,T4,T7

 LINE       20143
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T82,T85
1	1	1	Covered	T3,T4,T7

 LINE       20146
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       20149
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T74,T80,T83
1	1	1	Covered	T3,T4,T7

 LINE       20152
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T84
1	1	1	Covered	T3,T4,T7

 LINE       20179
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T86
1	1	1	Covered	T3,T4,T7

 LINE       20206
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20233
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T86
1	1	1	Covered	T3,T4,T7

 LINE       20260
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T84
1	1	1	Covered	T3,T4,T7

 LINE       20287
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T86
1	1	1	Covered	T3,T4,T7

 LINE       20314
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T80,T82,T85
1	1	1	Covered	T3,T4,T7

 LINE       20341
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T84,T83
1	1	1	Covered	T3,T4,T7

 LINE       20368
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T82,T85
1	1	1	Covered	T3,T4,T7

 LINE       20395
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20422
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       20449
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T80,T85,T87
1	1	1	Covered	T3,T4,T7

 LINE       20476
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T80,T83
1	1	1	Covered	T3,T4,T7

 LINE       20503
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T85
1	1	1	Covered	T3,T4,T7

 LINE       20530
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20557
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T3,T4,T7

 LINE       20584
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T82,T85
1	1	1	Covered	T3,T4,T7

 LINE       20611
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20638
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20665
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20692
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20719
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20746
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T3,T4,T7

 LINE       20773
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T74,T88,T89
1	1	1	Covered	T3,T4,T7

 LINE       20800
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T7,T13,T14

 LINE       20805
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T7,T13,T14

 LINE       20810
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T22
1	1	0	Covered	T77,T80,T84
1	1	1	Covered	T7,T14,T11

 LINE       20815
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T74,T77,T86
1	1	1	Covered	T7,T14,T11

 LINE       20820
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T6,T7,T10
1	1	0	Covered	T74,T77,T82
1	1	1	Covered	T6,T7,T10

 LINE       20831
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T10,T18
1	1	0	Covered	T77,T80,T86
1	1	1	Covered	T7,T10,T18

 LINE       20840
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T10,T18
1	1	0	Covered	T74,T82,T86
1	1	1	Covered	T7,T10,T18

 LINE       20843
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T10,T18
1	1	0	Covered	T74,T82,T84
1	1	1	Covered	T7,T10,T18

 LINE       20846
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T74,T77,T84
1	1	1	Covered	T7,T18,T21

 LINE       20849
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T21
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T7,T18,T21

 LINE       20852
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T80,T82,T84
1	1	1	Covered	T7,T18,T21

 LINE       20855
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T13
1	1	0	Covered	T74,T80,T89
1	1	1	Covered	T7,T18,T21

 LINE       20858
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T21
1	1	0	Covered	T74,T80,T84
1	1	1	Covered	T7,T18,T21

 LINE       20863
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T7,T18,T21
1	1	0	Covered	T74,T77,T80
1	1	1	Covered	T7,T18,T21

 LINE       20866
 EXPRESSION (addr_hit[71] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T18
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T18

 LINE       20867
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T6,T7,T18
1	1	0	Covered	T77,T80,T82
1	1	1	Covered	T6,T7,T18

 LINE       20870
 EXPRESSION (addr_hit[73] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T18
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T18