Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7329247	1			T1	189		T4	1		T5	1
all_values[1]	7329247	1			T1	189		T4	1		T5	1
all_values[2]	7329247	1			T1	189		T4	1		T5	1
all_values[3]	7329247	1			T1	189		T4	1		T5	1
all_values[4]	7329247	1			T1	189		T4	1		T5	1
all_values[5]	7329247	1			T1	189		T4	1		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42825045

1

T1

1134

T4

6

T5

6

auto[1]

1150437

1

T22

57

T30

27

T31

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43899801

1

T1

1129

T4

6

T5

6

auto[1]

75681

1

T1

5

T6

85

T7

895

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7120922	1			T1	189		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	43011	1			T6	47		T7	473		T11	395
all_values[0]	auto[1]	auto[0]	163619	1			T22	8		T30	4		T31	4
all_values[0]	auto[1]	auto[1]	1695	1			T22	3		T31	3		T45	2
all_values[1]	auto[0]	auto[0]	7069392	1			T1	189		T4	1		T5	1
all_values[1]	auto[0]	auto[1]	20257	1			T6	19		T7	288		T11	177
all_values[1]	auto[1]	auto[0]	238573	1			T22	8		T30	1		T31	2
all_values[1]	auto[1]	auto[1]	1025	1			T22	1		T31	2		T45	3
all_values[2]	auto[0]	auto[0]	7100607	1			T1	189		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	7936	1			T6	19		T7	134		T11	28
all_values[2]	auto[1]	auto[0]	220281	1			T22	9		T30	1		T31	4
all_values[2]	auto[1]	auto[1]	423	1			T22	2		T30	2		T31	1
all_values[3]	auto[0]	auto[0]	7292200	1			T1	189		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	189	1			T22	1		T30	2		T31	2
all_values[3]	auto[1]	auto[0]	36676	1			T22	7		T30	7		T31	4
all_values[3]	auto[1]	auto[1]	182	1			T22	4		T30	1		T31	3
all_values[4]	auto[0]	auto[0]	7178083	1			T1	189		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	206	1			T22	3		T30	2		T31	6
all_values[4]	auto[1]	auto[0]	150769	1			T22	3		T30	4		T31	1
all_values[4]	auto[1]	auto[1]	189	1			T22	7		T31	1		T45	2
all_values[5]	auto[0]	auto[0]	6991830	1			T1	184		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	412	1			T1	5		T59	2		T22	6
all_values[5]	auto[1]	auto[0]	336849	1			T22	3		T30	5		T31	6
all_values[5]	auto[1]	auto[1]	156	1			T22	2		T30	2		T31	1