Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	40624	1			T5	4		T6	35		T7	810
auto[SpiFlashAddrCfg]	9249	1			T5	4		T6	13		T7	129
auto[SpiFlashAddr3b]	11152	1			T6	17		T7	132		T15	2
auto[SpiFlashAddr4b]	9496	1			T5	4		T6	18		T7	154

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40733

1

T5

12

T6

53

T7

642

auto[1]

29788

1

T6

30

T7

583

T32

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37513

1

T5

6

T6

57

T7

588

auto[1]

33008

1

T5

6

T6

26

T7

637

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	46482	1			T5	4		T6	45		T7	880
values[1]	1300	1			T6	2		T7	21		T11	4
values[2]	1781	1			T6	3		T7	19		T11	9
values[3]	1760	1			T6	2		T7	30		T11	2
values[4]	1804	1			T6	3		T7	29		T15	2
values[5]	1760	1			T6	10		T7	35		T15	2
values[6]	1792	1			T7	30		T11	6		T35	10
values[7]	1819	1			T6	4		T7	39		T32	2
values[8]	12023	1			T5	8		T6	14		T7	142

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474

1

T5

12

T7

627

T13

28

auto[1]

39047

1

T6

83

T7

598

T11

218

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

67791

1

T5

12

T6

76

T7

1174

write

2730

1

T6

7

T7

51

T32

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24132

1

T5

4

T6

33

T7

303

valids[0x1]

46389

1

T5

8

T6

50

T7

922

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1935	1			T6	4		T7	19		T32	6
internal_process_ops[0x5a]	1930	1			T6	2		T7	36		T32	2
internal_process_ops[0x05]	23588	1			T6	5		T7	587		T17	2
internal_process_ops[0x35]	1973	1			T5	2		T6	7		T7	29
internal_process_ops[0x15]	1945	1			T6	1		T7	27		T11	7
internal_process_ops[0x03]	1328	1			T6	3		T7	20		T15	2
internal_process_ops[0x0b]	1261	1			T6	1		T7	13		T32	2
internal_process_ops[0x3b]	1280	1			T6	1		T7	19		T15	2
internal_process_ops[0x6b]	1267	1			T6	4		T7	15		T14	6
internal_process_ops[0xbb]	1225	1			T7	15		T11	1		T68	4
internal_process_ops[0xeb]	1310	1			T5	2		T6	3		T7	19

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69203

1

T5

12

T6

79

T7

1199

auto[1]

1318

1

T6

4

T7

26

T32

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67910

1

T5

12

T6

81

T7

1180

auto[1]

2611

1

T6

2

T7

45

T11

20

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10703

1

T5

4

T7

139

T13

28

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6413

1

T7

265

T32

12

T22

50

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2259

1

T5

4

T7

22

T15

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1838

1

T7

36

T22

33

T30

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2674

1

T7

37

T15

2

T68

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2239

1

T7

31

T32

4

T22

34

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2205

1

T5

4

T7

41

T14

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2066

1

T7

41

T32

2

T22

38

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

77

1

T28

4

T23

1

T58

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T7

3

T31

2

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

58

1

T7

3

T22

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

75

1

T7

3

T32

2

T22

7

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T36

1

T145

8

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

46

1

T7

1

T30

2

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

49

1

T23

2

T36

1

T57

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T7

1

T22

1

T146

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T28

2

T22

1

T31

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

46

1

T31

1

T38

3

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

52

1

T7

1

T39

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

75

1

T22

5

T36

1

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

70

1

T22

2

T31

1

T58

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T7

2

T22

4

T30

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T22

5

T23

7

T31

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

86

1

T7

1

T22

4

T31

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13983

1

T6

25

T7

287

T11

76

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8850

1

T6

10

T7

92

T11

35

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2338

1

T6

11

T7

33

T11

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2162

1

T6

1

T7

28

T11

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2905

1

T6

8

T7

29

T11

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2652

1

T6

5

T7

30

T11

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2272

1

T6

8

T7

33

T11

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2232

1

T6

8

T7

30

T11

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T7

2

T56

1

T147

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T7

7

T31

3

T148

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

108

1

T7

9

T11

1

T29

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T11

1

T147

1

T149

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T6

1

T11

4

T31

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T7

3

T31

2

T56

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T7

2

T31

1

T56

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T7

3

T31

2

T56

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T11

1

T80

1

T147

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

113

1

T7

1

T11

2

T31

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T7

2

T11

2

T56

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T6

4

T7

1

T29

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T7

2

T11

2

T148

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T27

1

T56

2

T80

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T6

2

T7

4

T11

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T31

2

T148

2

T56

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4205	1			T5	2		T7	54		T13	28
auto[0]	values[0]	valids[0x1]	15760	1			T5	2		T7	388		T17	2
auto[0]	values[1]	valids[0x1]	580	1			T7	7		T34	6		T22	11
auto[0]	values[2]	valids[0x0]	529	1			T7	8		T68	4		T22	2
auto[0]	values[2]	valids[0x1]	297	1			T7	6		T150	2		T22	3
auto[0]	values[3]	valids[0x0]	546	1			T7	5		T22	8		T30	5
auto[0]	values[3]	valids[0x1]	295	1			T7	7		T151	2		T22	5
auto[0]	values[4]	valids[0x0]	532	1			T7	8		T15	2		T79	2
auto[0]	values[4]	valids[0x1]	305	1			T7	5		T22	11		T30	2
auto[0]	values[5]	valids[0x0]	568	1			T7	18		T34	4		T35	4
auto[0]	values[5]	valids[0x1]	283	1			T7	5		T15	2		T22	2
auto[0]	values[6]	valids[0x0]	589	1			T7	11		T35	10		T22	21
auto[0]	values[6]	valids[0x1]	300	1			T7	4		T22	2		T30	1
auto[0]	values[7]	valids[0x0]	549	1			T7	16		T28	4		T150	4
auto[0]	values[7]	valids[0x1]	346	1			T7	7		T32	2		T68	8
auto[0]	values[8]	valids[0x0]	3553	1			T5	2		T7	40		T14	6
auto[0]	values[8]	valids[0x1]	2237	1			T5	6		T7	38		T17	2
auto[1]	values[0]	valids[0x0]	5988	1			T6	14		T7	62		T11	38
auto[1]	values[0]	valids[0x1]	20529	1			T6	31		T7	376		T11	108
auto[1]	values[1]	valids[0x1]	720	1			T6	2		T7	14		T11	4
auto[1]	values[2]	valids[0x0]	579	1			T6	2		T7	1		T11	2
auto[1]	values[2]	valids[0x1]	376	1			T6	1		T7	4		T11	7
auto[1]	values[3]	valids[0x0]	576	1			T7	10		T11	1		T29	3
auto[1]	values[3]	valids[0x1]	343	1			T6	2		T7	8		T11	1
auto[1]	values[4]	valids[0x0]	596	1			T6	1		T7	5		T11	3
auto[1]	values[4]	valids[0x1]	371	1			T6	2		T7	11		T11	1
auto[1]	values[5]	valids[0x0]	525	1			T6	3		T7	5		T11	4
auto[1]	values[5]	valids[0x1]	384	1			T6	7		T7	7		T11	1
auto[1]	values[6]	valids[0x0]	558	1			T7	14		T11	2		T29	2
auto[1]	values[6]	valids[0x1]	345	1			T7	1		T11	4		T31	3
auto[1]	values[7]	valids[0x0]	531	1			T6	3		T7	7		T11	4
auto[1]	values[7]	valids[0x1]	393	1			T6	1		T7	9		T11	6
auto[1]	values[8]	valids[0x0]	3708	1			T6	10		T7	39		T11	18
auto[1]	values[8]	valids[0x1]	2525	1			T6	4		T7	25		T11	14