Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19901

1

T5

1

T6

31

T7

270

auto[1]

23866

1

T6

5

T7

600

T11

57

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16735

1

T5

1

T6

23

T7

227

auto[1]

27032

1

T6

13

T7

643

T17

2

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6975	1			T5	1		T6	23		T7	174
auto[524288:1048575]	4999	1			T6	2		T7	64		T13	2
auto[1048576:1572863]	4882	1			T7	35		T14	2		T11	37
auto[1572864:2097151]	5493	1			T6	3		T7	149		T13	1
auto[2097152:2621439]	5151	1			T6	7		T7	95		T13	2
auto[2621440:3145727]	5356	1			T6	1		T7	94		T13	3
auto[3145728:3670015]	5857	1			T7	133		T11	20		T68	5
auto[3670016:4194303]	5054	1			T7	126		T14	1		T11	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42716

1

T5

1

T6

36

T7

836

auto[1]

1051

1

T7

34

T11

2

T28

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34726

1

T5

1

T6

29

T7

752

auto[1]

9041

1

T6

7

T7

118

T13

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1998	1			T5	1		T6	9		T7	26
auto[0]	auto[0]	auto[0:524287]	auto[1]	799	1			T6	7		T7	12		T17	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1406	1			T7	14		T13	2		T14	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	528	1			T7	2		T11	4		T68	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1338	1			T7	19		T14	2		T11	12
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	491	1			T7	5		T11	4		T68	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1322	1			T6	2		T7	10		T13	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	585	1			T6	1		T7	6		T11	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1411	1			T6	4		T7	20		T13	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	586	1			T7	6		T68	1		T153	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1312	1			T7	24		T13	3		T14	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	468	1			T6	1		T7	7		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1299	1			T7	16		T11	3		T68	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	527	1			T7	9		T11	1		T68	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1357	1			T7	16		T14	1		T68	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	512	1			T7	9		T68	1		T69	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	342	1			T6	1		T7	4		T13	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	152	1			T6	1		T7	3		T23	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	298	1			T6	2		T22	2		T23	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	155	1			T7	1		T22	1		T23	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	314	1			T33	1		T22	10		T30	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	132	1			T7	1		T22	2		T31	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	326	1			T7	15		T11	2		T33	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	180	1			T7	19		T11	2		T30	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	304	1			T6	3		T7	1		T11	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	137	1			T11	1		T22	5		T29	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	344	1			T7	4		T22	9		T31	9
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	151	1			T7	2		T29	1		T31	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	389	1			T7	8		T11	4		T22	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	184	1			T7	2		T11	6		T30	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	363	1			T7	5		T33	3		T22	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	191	1			T7	4		T11	2		T22	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	361	1			T6	2		T7	8		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2870	1			T6	3		T7	121		T11	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	257	1			T7	4		T11	3		T22	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1759	1			T7	43		T11	8		T22	35
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	245	1			T7	2		T11	8		T22	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1680	1			T7	8		T11	13		T22	82
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	230	1			T7	4		T22	2		T23	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2264	1			T7	78		T22	52		T23	39
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	277	1			T7	3		T11	3		T30	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1855	1			T7	65		T11	3		T30	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	248	1			T7	4		T11	2		T22	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2277	1			T7	50		T11	6		T22	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	252	1			T7	8		T11	1		T22	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2317	1			T7	64		T11	1		T22	75
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	227	1			T7	6		T22	2		T30	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1668	1			T7	83		T22	9		T30	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	49	1			T23	1		T31	3		T56	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	404	1			T23	6		T31	3		T56	57
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	59	1			T31	2		T80	3		T38	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	537	1			T31	4		T80	12		T38	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	57	1			T22	3		T30	2		T31	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	625	1			T22	38		T30	2		T31	27
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	62	1			T7	3		T30	1		T149	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	524	1			T7	14		T30	1		T149	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	61	1			T22	2		T30	2		T36	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	520	1			T22	99		T30	3		T36	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	67	1			T7	1		T31	4		T258	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	489	1			T7	2		T31	6		T258	80
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T7	1		T11	2		T30	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	811	1			T7	25		T11	2		T30	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	82	1			T7	1		T22	2		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	654	1			T7	2		T22	14		T31	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15555	1			T5	1		T6	24		T7	182
auto[0]	auto[0]	auto[1]	384	1			T7	19		T28	4		T34	1
auto[0]	auto[1]	auto[0]	3859	1			T6	7		T7	68		T13	3
auto[0]	auto[1]	auto[1]	103	1			T7	1		T22	2		T31	3
auto[1]	auto[0]	auto[0]	18348	1			T6	5		T7	538		T11	52
auto[1]	auto[0]	auto[1]	439	1			T7	13		T11	1		T22	5
auto[1]	auto[1]	auto[0]	4954	1			T7	48		T11	3		T22	156
auto[1]	auto[1]	auto[1]	125	1			T7	1		T11	1		T22	2