Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18382

1

T5

12

T7

245

T13

28

auto[1]

13092

1

T7

382

T32

20

T22

178

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4186	1			T7	84		T33	16		T22	40
values[1]	4414	1			T7	174		T15	8		T151	4
values[2]	4112	1			T22	232		T30	20		T23	188
values[3]	3884	1			T5	12		T7	182		T69	10
values[4]	3973	1			T7	20		T32	20		T22	164
values[5]	3296	1			T7	20		T13	28		T17	4
values[6]	3691	1			T7	65		T34	93		T153	4
values[7]	3918	1			T7	82		T14	6		T68	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4413	1			T7	42		T15	8		T17	4
values[1]	3780	1			T7	169		T151	4		T22	328
values[2]	3014	1			T7	125		T14	6		T22	20
values[3]	3776	1			T5	12		T7	66		T79	12
values[4]	4344	1			T7	57		T13	28		T68	24
values[5]	3677	1			T7	25		T32	20		T22	20
values[6]	4420	1			T7	60		T150	14		T34	93
values[7]	4050	1			T7	83		T22	40		T30	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	277	1			T7	9		T36	11		T37	11
auto[0]	values[0]	values[1]	332	1			T36	9		T159	10		T179	9
auto[0]	values[0]	values[2]	164	1			T30	14		T36	8		T170	7
auto[0]	values[0]	values[3]	179	1			T22	10		T37	9		T170	48
auto[0]	values[0]	values[4]	410	1			T33	16		T31	13		T170	11
auto[0]	values[0]	values[5]	314	1			T39	8		T259	8		T170	15
auto[0]	values[0]	values[6]	450	1			T30	16		T176	18		T156	11
auto[0]	values[0]	values[7]	391	1			T7	37		T22	12		T160	6
auto[0]	values[1]	values[0]	370	1			T15	8		T22	7		T31	9
auto[0]	values[1]	values[1]	429	1			T7	10		T151	4		T22	88
auto[0]	values[1]	values[2]	188	1			T30	22		T37	12		T145	32
auto[0]	values[1]	values[3]	444	1			T7	12		T22	8		T31	122
auto[0]	values[1]	values[4]	283	1			T30	14		T36	11		T165	59
auto[0]	values[1]	values[5]	136	1			T184	12		T178	14		T190	11
auto[0]	values[1]	values[6]	583	1			T22	16		T38	18		T174	2
auto[0]	values[1]	values[7]	290	1			T7	32		T39	12		T144	53
auto[0]	values[2]	values[0]	434	1			T23	174		T37	15		T207	12
auto[0]	values[2]	values[1]	388	1			T22	203		T37	18		T40	59
auto[0]	values[2]	values[2]	195	1			T31	16		T38	9		T259	15
auto[0]	values[2]	values[3]	314	1			T30	10		T39	11		T184	13
auto[0]	values[2]	values[4]	141	1			T31	15		T38	16		T144	9
auto[0]	values[2]	values[5]	221	1			T31	10		T37	9		T119	4
auto[0]	values[2]	values[6]	285	1			T22	14		T39	22		T184	9
auto[0]	values[2]	values[7]	254	1			T31	8		T144	19		T260	43
auto[0]	values[3]	values[0]	361	1			T69	10		T35	26		T31	17
auto[0]	values[3]	values[1]	188	1			T37	12		T38	9		T146	15
auto[0]	values[3]	values[2]	209	1			T7	6		T141	4		T39	15
auto[0]	values[3]	values[3]	170	1			T5	12		T163	8		T39	15
auto[0]	values[3]	values[4]	262	1			T7	10		T23	12		T184	14
auto[0]	values[3]	values[5]	274	1			T39	81		T261	4		T262	24
auto[0]	values[3]	values[6]	398	1			T7	15		T22	77		T31	24
auto[0]	values[3]	values[7]	328	1			T22	11		T170	20		T185	22
auto[0]	values[4]	values[0]	351	1			T30	14		T23	34		T37	26
auto[0]	values[4]	values[1]	183	1			T156	12		T164	9		T165	13
auto[0]	values[4]	values[2]	257	1			T7	16		T22	10		T31	12
auto[0]	values[4]	values[3]	377	1			T183	18		T180	34		T38	19
auto[0]	values[4]	values[4]	315	1			T22	12		T23	9		T37	10
auto[0]	values[4]	values[5]	183	1			T31	14		T36	5		T186	10
auto[0]	values[4]	values[6]	324	1			T22	108		T245	52		T205	19
auto[0]	values[4]	values[7]	357	1			T30	15		T40	91		T164	13
auto[0]	values[5]	values[0]	187	1			T17	4		T22	57		T164	18
auto[0]	values[5]	values[1]	242	1			T152	24		T37	15		T40	13
auto[0]	values[5]	values[2]	149	1			T40	10		T263	28		T186	9
auto[0]	values[5]	values[3]	212	1			T79	12		T31	12		T39	7
auto[0]	values[5]	values[4]	466	1			T13	28		T28	128		T37	43
auto[0]	values[5]	values[5]	252	1			T36	14		T264	18		T146	22
auto[0]	values[5]	values[6]	157	1			T7	14		T150	14		T39	19
auto[0]	values[5]	values[7]	154	1			T185	25		T206	24		T195	16
auto[0]	values[6]	values[0]	232	1			T23	8		T184	14		T259	8
auto[0]	values[6]	values[1]	275	1			T7	22		T22	10		T30	10
auto[0]	values[6]	values[2]	245	1			T39	10		T40	41		T164	12
auto[0]	values[6]	values[3]	237	1			T153	4		T31	11		T256	42
auto[0]	values[6]	values[4]	167	1			T31	9		T57	24		T194	8
auto[0]	values[6]	values[5]	247	1			T7	9		T37	10		T40	25
auto[0]	values[6]	values[6]	272	1			T34	93		T22	22		T57	15
auto[0]	values[6]	values[7]	377	1			T31	11		T78	24		T39	11
auto[0]	values[7]	values[0]	381	1			T31	43		T40	15		T265	6
auto[0]	values[7]	values[1]	263	1			T7	34		T214	14		T178	46
auto[0]	values[7]	values[2]	256	1			T14	6		T123	2		T146	9
auto[0]	values[7]	values[3]	238	1			T7	4		T182	2		T200	12
auto[0]	values[7]	values[4]	343	1			T68	24		T31	66		T57	10
auto[0]	values[7]	values[5]	354	1			T22	12		T188	22		T40	7
auto[0]	values[7]	values[6]	285	1			T7	15		T22	13		T39	36
auto[0]	values[7]	values[7]	382	1			T30	18		T158	8		T266	10
auto[1]	values[0]	values[0]	272	1			T7	33		T36	11		T37	9
auto[1]	values[0]	values[1]	90	1			T36	11		T179	11		T200	5
auto[1]	values[0]	values[2]	178	1			T30	6		T36	12		T122	16
auto[1]	values[0]	values[3]	99	1			T22	10		T37	11		T170	21
auto[1]	values[0]	values[4]	245	1			T31	11		T170	13		T229	23
auto[1]	values[0]	values[5]	384	1			T39	49		T259	12		T170	8
auto[1]	values[0]	values[6]	235	1			T30	4		T156	9		T259	13
auto[1]	values[0]	values[7]	166	1			T7	5		T22	8		T38	7
auto[1]	values[1]	values[0]	289	1			T22	13		T31	54		T39	18
auto[1]	values[1]	values[1]	293	1			T7	77		T22	8		T146	6
auto[1]	values[1]	values[2]	166	1			T30	3		T37	8		T219	17
auto[1]	values[1]	values[3]	275	1			T7	34		T22	17		T31	4
auto[1]	values[1]	values[4]	230	1			T30	10		T36	11		T165	11
auto[1]	values[1]	values[5]	64	1			T184	15		T178	6		T190	9
auto[1]	values[1]	values[6]	200	1			T22	9		T38	7		T164	12
auto[1]	values[1]	values[7]	174	1			T7	9		T39	10		T144	9
auto[1]	values[2]	values[0]	231	1			T23	14		T37	30		T207	8
auto[1]	values[2]	values[1]	196	1			T22	9		T55	10		T37	22
auto[1]	values[2]	values[2]	154	1			T31	15		T38	11		T259	5
auto[1]	values[2]	values[3]	401	1			T30	10		T39	78		T184	7
auto[1]	values[2]	values[4]	109	1			T31	7		T38	9		T144	11
auto[1]	values[2]	values[5]	341	1			T31	15		T37	11		T40	31
auto[1]	values[2]	values[6]	173	1			T22	6		T39	18		T184	19
auto[1]	values[2]	values[7]	275	1			T31	13		T144	24		T162	24
auto[1]	values[3]	values[0]	199	1			T31	8		T39	6		T184	76
auto[1]	values[3]	values[1]	335	1			T37	12		T38	11		T172	12
auto[1]	values[3]	values[2]	261	1			T7	99		T39	5		T184	11
auto[1]	values[3]	values[3]	99	1			T39	5		T144	13		T156	9
auto[1]	values[3]	values[4]	251	1			T7	47		T23	8		T184	16
auto[1]	values[3]	values[5]	120	1			T39	5		T165	7		T267	26
auto[1]	values[3]	values[6]	246	1			T7	5		T22	3		T31	20
auto[1]	values[3]	values[7]	183	1			T22	9		T170	7		T185	3
auto[1]	values[4]	values[0]	221	1			T30	7		T23	21		T37	37
auto[1]	values[4]	values[1]	149	1			T156	8		T164	11		T192	20
auto[1]	values[4]	values[2]	118	1			T7	4		T22	10		T31	12
auto[1]	values[4]	values[3]	232	1			T38	5		T39	20		T219	7
auto[1]	values[4]	values[4]	409	1			T22	13		T23	73		T37	52
auto[1]	values[4]	values[5]	193	1			T32	20		T31	6		T36	15
auto[1]	values[4]	values[6]	186	1			T22	11		T245	6		T205	9
auto[1]	values[4]	values[7]	118	1			T30	5		T40	4		T164	16
auto[1]	values[5]	values[0]	124	1			T22	12		T164	7		T165	9
auto[1]	values[5]	values[1]	135	1			T37	5		T40	7		T164	7
auto[1]	values[5]	values[2]	80	1			T40	32		T186	11		T206	8
auto[1]	values[5]	values[3]	185	1			T31	8		T39	13		T40	26
auto[1]	values[5]	values[4]	329	1			T37	17		T156	9		T181	8
auto[1]	values[5]	values[5]	169	1			T36	8		T146	7		T181	25
auto[1]	values[5]	values[6]	219	1			T7	6		T39	21		T184	10
auto[1]	values[5]	values[7]	236	1			T185	6		T206	11		T195	6
auto[1]	values[6]	values[0]	203	1			T23	23		T184	12		T259	12
auto[1]	values[6]	values[1]	163	1			T7	18		T22	10		T30	14
auto[1]	values[6]	values[2]	221	1			T39	89		T40	3		T164	8
auto[1]	values[6]	values[3]	193	1			T31	11		T146	15		T170	10
auto[1]	values[6]	values[4]	158	1			T31	48		T57	33		T184	24
auto[1]	values[6]	values[5]	237	1			T7	16		T37	10		T40	8
auto[1]	values[6]	values[6]	242	1			T22	6		T57	7		T40	26
auto[1]	values[6]	values[7]	222	1			T31	22		T171	16		T39	87
auto[1]	values[7]	values[0]	281	1			T31	10		T40	12		T170	8
auto[1]	values[7]	values[1]	119	1			T7	8		T214	6		T178	8
auto[1]	values[7]	values[2]	173	1			T146	11		T208	16		T166	17
auto[1]	values[7]	values[3]	121	1			T7	16		T200	8		T213	10
auto[1]	values[7]	values[4]	226	1			T31	12		T57	10		T181	16
auto[1]	values[7]	values[5]	188	1			T22	8		T40	26		T144	12
auto[1]	values[7]	values[6]	165	1			T7	5		T22	16		T39	5
auto[1]	values[7]	values[7]	143	1			T30	2		T161	4		T230	11