Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	449	1			T7	2		T14	2		T68	4
auto[ReadAddrCrossIntoMailbox]	309	1			T7	5		T14	2		T22	8
auto[ReadAddrCrossOutOfMailbox]	337	1			T7	3		T79	2		T22	4
auto[ReadAddrCrossAllMailbox]	252	1			T7	3		T14	2		T79	2
auto[ReadAddrOutsideMailbox]	3672	1			T5	2		T7	64		T15	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2537

1

T5

1

T7

34

T14

3

auto[1]

2482

1

T5

1

T7

43

T14

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	897	1			T7	12		T15	2		T22	14
read_ops[0x0b]	814	1			T7	11		T68	6		T79	6
read_ops[0x3b]	847	1			T7	12		T15	2		T34	4
read_ops[0x6b]	823	1			T7	13		T14	6		T15	2
read_ops[0xbb]	780	1			T7	13		T68	4		T35	4
read_ops[0xeb]	858	1			T5	2		T7	16		T32	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T30	1		T152	1		T37	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T22	1		T152	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T23	1		T158	1		T144	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T7	1		T36	2		T158	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T22	1		T30	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T22	1		T40	1		T164	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T30	1		T40	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T7	1		T259	1		T179	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	349	1			T7	6		T15	1		T22	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T7	4		T15	1		T22	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T22	1		T152	1		T31	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T7	1		T30	3		T152	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T7	2		T22	2		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T22	1		T31	2		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T36	1		T39	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T30	1		T31	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T7	1		T158	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T7	1		T158	1		T156	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T7	3		T68	3		T79	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T7	3		T68	3		T79	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T22	1		T152	1		T37	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T152	1		T37	2		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T22	1		T31	1		T37	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T30	1		T37	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T144	1		T170	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T22	1		T39	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T30	2		T40	1		T156	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T40	1		T164	1		T246	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	319	1			T7	6		T15	1		T34	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T7	6		T15	1		T34	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T14	1		T152	2		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T7	1		T14	1		T152	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T14	1		T22	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T7	1		T14	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T30	1		T36	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T7	1		T40	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	35	1			T14	1		T22	1		T23	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T14	1		T31	1		T38	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T7	2		T15	1		T150	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T7	8		T15	1		T150	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T68	2		T152	1		T23	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T68	2		T22	2		T152	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T22	1		T37	3		T219	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T38	1		T164	1		T170	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T22	1		T36	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T37	1		T40	1		T146	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T31	2		T39	1		T144	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T22	1		T23	1		T40	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T7	6		T35	2		T22	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T7	7		T35	2		T22	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T152	1		T31	1		T40	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T22	2		T152	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T22	1		T31	3		T39	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T7	1		T22	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T7	1		T79	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T7	1		T79	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T79	1		T31	2		T146	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T79	1		T39	1		T156	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T5	1		T7	7		T32	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T5	1		T7	6		T32	1