Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7329247	1			T1	189		T4	1		T5	1
all_pins[1]	7329247	1			T1	189		T4	1		T5	1
all_pins[2]	7329247	1			T1	189		T4	1		T5	1
all_pins[3]	7329247	1			T1	189		T4	1		T5	1
all_pins[4]	7329247	1			T1	189		T4	1		T5	1
all_pins[5]	7329247	1			T1	189		T4	1		T5	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43966493	1			T1	1134		T4	6		T5	6
values[0x1]	8989	1			T22	19		T30	5		T31	11
transitions[0x0=>0x1]	7921	1			T22	15		T30	4		T31	8
transitions[0x1=>0x0]	7941	1			T22	15		T30	4		T31	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7327487	1			T1	189		T4	1		T5	1
all_pins[0]	values[0x1]	1760	1			T22	3		T31	3		T45	2
all_pins[0]	transitions[0x0=>0x1]	1081	1			T22	3		T31	2		T37	1
all_pins[0]	transitions[0x1=>0x0]	388	1			T22	1		T31	1		T45	1
all_pins[1]	values[0x0]	7328180	1			T1	189		T4	1		T5	1
all_pins[1]	values[0x1]	1067	1			T22	1		T31	2		T45	3
all_pins[1]	transitions[0x0=>0x1]	906	1			T31	1		T45	3		T57	2
all_pins[1]	transitions[0x1=>0x0]	276	1			T22	1		T30	2		T57	18
all_pins[2]	values[0x0]	7328810	1			T1	189		T4	1		T5	1
all_pins[2]	values[0x1]	437	1			T22	2		T30	2		T31	1
all_pins[2]	transitions[0x0=>0x1]	397	1			T22	2		T30	1		T57	19
all_pins[2]	transitions[0x1=>0x0]	142	1			T22	4		T31	2		T57	1
all_pins[3]	values[0x0]	7329065	1			T1	189		T4	1		T5	1
all_pins[3]	values[0x1]	182	1			T22	4		T30	1		T31	3
all_pins[3]	transitions[0x0=>0x1]	134	1			T22	2		T30	1		T31	3
all_pins[3]	transitions[0x1=>0x0]	141	1			T22	5		T31	1		T45	2
all_pins[4]	values[0x0]	7329058	1			T1	189		T4	1		T5	1
all_pins[4]	values[0x1]	189	1			T22	7		T31	1		T45	2
all_pins[4]	transitions[0x0=>0x1]	159	1			T22	6		T31	1		T45	1
all_pins[4]	transitions[0x1=>0x0]	5324	1			T22	1		T30	2		T31	1
all_pins[5]	values[0x0]	7323893	1			T1	189		T4	1		T5	1
all_pins[5]	values[0x1]	5354	1			T22	2		T30	2		T31	1
all_pins[5]	transitions[0x0=>0x1]	5244	1			T22	2		T30	2		T31	1
all_pins[5]	transitions[0x1=>0x0]	1670	1			T22	3		T31	3		T45	2