Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3654	1			T7	103		T22	100		T31	44
values[1]	4260	1			T7	87		T68	24		T33	16
values[2]	3725	1			T7	165		T15	8		T32	20
values[3]	3492	1			T22	74		T30	45		T152	24
values[4]	4145	1			T7	102		T28	128		T150	14
values[5]	4326	1			T35	26		T22	124		T23	82
values[6]	3158	1			T5	12		T14	6		T17	4
values[7]	4714	1			T7	170		T13	28		T153	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3445	1			T7	61		T32	20		T33	16
values[1]	3920	1			T5	12		T7	173		T68	24
values[2]	3913	1			T7	99		T15	8		T79	12
values[3]	4054	1			T17	4		T22	267		T23	231
values[4]	4056	1			T7	107		T13	28		T22	212
values[5]	3439	1			T7	42		T22	165		T23	70
values[6]	4736	1			T7	40		T22	60		T23	20
values[7]	3911	1			T7	105		T14	6		T150	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30964

1

T5

12

T7

616

T13

28

auto[1]

510

1

T7

11

T32

2

T22

21

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[6]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	531	1			T7	41		T31	20		T57	22
auto[0]	values[0]	values[1]	326	1			T39	20		T154	60		T155	21
auto[0]	values[0]	values[2]	398	1			T7	42		T40	30		T156	20
auto[0]	values[0]	values[3]	486	1			T22	20		T31	22		T40	44
auto[0]	values[0]	values[4]	411	1			T38	20		T39	29		T144	20
auto[0]	values[0]	values[5]	427	1			T22	80		T36	22		T55	10
auto[0]	values[0]	values[6]	469	1			T7	18		T57	20		T157	16
auto[0]	values[0]	values[7]	553	1			T37	18		T38	23		T40	33
auto[0]	values[1]	values[0]	309	1			T33	16		T151	4		T31	57
auto[0]	values[1]	values[1]	663	1			T7	84		T68	24		T31	31
auto[0]	values[1]	values[2]	429	1			T36	17		T38	20		T39	89
auto[0]	values[1]	values[3]	791	1			T31	40		T78	24		T158	8
auto[0]	values[1]	values[4]	524	1			T30	25		T37	45		T39	40
auto[0]	values[1]	values[5]	563	1			T159	10		T57	37		T37	21
auto[0]	values[1]	values[6]	610	1			T23	20		T160	6		T38	24
auto[0]	values[1]	values[7]	302	1			T36	19		T146	19		T161	4
auto[0]	values[2]	values[0]	318	1			T32	18		T38	22		T144	21
auto[0]	values[2]	values[1]	429	1			T7	20		T31	53		T162	24
auto[0]	values[2]	values[2]	511	1			T15	8		T79	12		T30	20
auto[0]	values[2]	values[3]	598	1			T23	149		T141	4		T163	8
auto[0]	values[2]	values[4]	549	1			T7	20		T30	20		T123	2
auto[0]	values[2]	values[5]	203	1			T164	23		T165	20		T166	19
auto[0]	values[2]	values[6]	449	1			T7	20		T167	8		T168	10
auto[0]	values[2]	values[7]	604	1			T7	102		T58	24		T39	39
auto[0]	values[3]	values[0]	421	1			T169	20		T146	20		T170	20
auto[0]	values[3]	values[1]	430	1			T31	21		T39	20		T144	20
auto[0]	values[3]	values[2]	518	1			T152	24		T171	16		T172	12
auto[0]	values[3]	values[3]	238	1			T22	29		T31	17		T173	20
auto[0]	values[3]	values[4]	452	1			T37	20		T144	23		T174	2
auto[0]	values[3]	values[5]	392	1			T22	24		T31	33		T57	20
auto[0]	values[3]	values[6]	520	1			T22	20		T31	61		T36	19
auto[0]	values[3]	values[7]	456	1			T30	39		T121	22		T175	26
auto[0]	values[4]	values[0]	309	1			T7	20		T30	19		T38	20
auto[0]	values[4]	values[1]	585	1			T7	20		T28	128		T176	18
auto[0]	values[4]	values[2]	431	1			T30	20		T23	35		T37	20
auto[0]	values[4]	values[3]	493	1			T156	20		T170	20		T177	24
auto[0]	values[4]	values[4]	649	1			T7	20		T22	205		T23	20
auto[0]	values[4]	values[5]	476	1			T7	41		T37	20		T38	23
auto[0]	values[4]	values[6]	523	1			T165	106		T178	27		T179	24
auto[0]	values[4]	values[7]	604	1			T150	14		T22	117		T180	34
auto[0]	values[5]	values[0]	479	1			T35	26		T37	23		T170	24
auto[0]	values[5]	values[1]	421	1			T39	56		T181	31		T182	2
auto[0]	values[5]	values[2]	676	1			T31	23		T39	20		T40	43
auto[0]	values[5]	values[3]	748	1			T22	120		T23	81		T37	20
auto[0]	values[5]	values[4]	484	1			T36	21		T39	20		T156	32
auto[0]	values[5]	values[5]	443	1			T31	22		T183	18		T39	18
auto[0]	values[5]	values[6]	627	1			T40	55		T184	29		T146	25
auto[0]	values[5]	values[7]	373	1			T31	22		T184	20		T165	32
auto[0]	values[6]	values[0]	445	1			T185	20		T186	20		T187	14
auto[0]	values[6]	values[1]	383	1			T5	12		T30	20		T122	16
auto[0]	values[6]	values[2]	218	1			T69	10		T30	22		T188	22
auto[0]	values[6]	values[3]	387	1			T17	4		T22	92		T37	19
auto[0]	values[6]	values[4]	255	1			T189	18		T179	60		T190	20
auto[0]	values[6]	values[5]	374	1			T22	39		T23	70		T37	40
auto[0]	values[6]	values[6]	615	1			T22	20		T145	32		T184	20
auto[0]	values[6]	values[7]	446	1			T14	6		T34	93		T22	20
auto[0]	values[7]	values[0]	575	1			T39	20		T144	21		T184	18
auto[0]	values[7]	values[1]	622	1			T7	45		T191	6		T39	99
auto[0]	values[7]	values[2]	650	1			T7	56		T22	22		T39	19
auto[0]	values[7]	values[3]	250	1			T144	19		T192	20		T193	8
auto[0]	values[7]	values[4]	680	1			T7	67		T13	28		T31	124
auto[0]	values[7]	values[5]	497	1			T22	20		T31	25		T164	20
auto[0]	values[7]	values[6]	857	1			T22	19		T31	74		T36	22
auto[0]	values[7]	values[7]	509	1			T153	4		T194	8		T40	31
auto[1]	values[0]	values[0]	10	1			T184	2		T185	2		T195	1
auto[1]	values[0]	values[1]	2	1			T154	1		T196	1		-	-
auto[1]	values[0]	values[2]	10	1			T40	3		T179	1		T155	1
auto[1]	values[0]	values[3]	8	1			T31	2		T197	1		T198	2
auto[1]	values[0]	values[4]	7	1			T39	1		T164	2		T155	1
auto[1]	values[0]	values[5]	2	1			T186	1		T166	1		-	-
auto[1]	values[0]	values[6]	9	1			T7	2		T40	1		T199	2
auto[1]	values[0]	values[7]	5	1			T37	2		T38	1		T200	1
auto[1]	values[1]	values[0]	6	1			T178	1		T186	2		T197	2
auto[1]	values[1]	values[1]	9	1			T7	3		T179	1		T201	1
auto[1]	values[1]	values[2]	11	1			T36	3		T197	3		T202	1
auto[1]	values[1]	values[3]	5	1			T154	1		T203	1		T204	1
auto[1]	values[1]	values[4]	6	1			T39	1		T164	1		T205	2
auto[1]	values[1]	values[5]	15	1			T40	5		T205	1		T206	2
auto[1]	values[1]	values[6]	11	1			T38	1		T207	1		T170	1
auto[1]	values[1]	values[7]	6	1			T36	1		T146	1		T208	1
auto[1]	values[2]	values[0]	9	1			T32	2		T144	2		T200	2
auto[1]	values[2]	values[1]	12	1			T209	4		T205	2		T210	1
auto[1]	values[2]	values[2]	5	1			T178	2		T196	2		T195	1
auto[1]	values[2]	values[3]	10	1			T184	1		T164	1		T211	4
auto[1]	values[2]	values[4]	6	1			T170	1		T201	1		T212	1
auto[1]	values[2]	values[5]	5	1			T166	1		T213	1		T212	1
auto[1]	values[2]	values[7]	17	1			T7	3		T39	1		T164	1
auto[1]	values[3]	values[0]	6	1			T165	2		T166	1		T200	1
auto[1]	values[3]	values[1]	14	1			T31	1		T179	2		T206	1
auto[1]	values[3]	values[2]	8	1			T214	2		T200	2		T63	2
auto[1]	values[3]	values[3]	8	1			T31	4		T215	2		T216	2
auto[1]	values[3]	values[4]	7	1			T170	3		T217	1		T210	1
auto[1]	values[3]	values[5]	10	1			T22	1		T38	1		T208	2
auto[1]	values[3]	values[6]	5	1			T31	2		T36	1		T210	1
auto[1]	values[3]	values[7]	7	1			T30	6		T218	1		-	-
auto[1]	values[4]	values[0]	5	1			T30	1		T170	3		T219	1
auto[1]	values[4]	values[1]	7	1			T170	1		T165	2		T220	1
auto[1]	values[4]	values[2]	8	1			T146	1		T165	2		T178	1
auto[1]	values[4]	values[3]	9	1			T178	2		T166	2		T221	3
auto[1]	values[4]	values[4]	12	1			T22	7		T222	3		T223	2
auto[1]	values[4]	values[5]	7	1			T7	1		T38	2		T224	2
auto[1]	values[4]	values[6]	11	1			T165	2		T225	4		T210	1
auto[1]	values[4]	values[7]	16	1			T22	2		T164	1		T219	3
auto[1]	values[5]	values[0]	8	1			T170	1		T63	1		T204	3
auto[1]	values[5]	values[1]	3	1			T39	1		T166	1		T226	1
auto[1]	values[5]	values[2]	16	1			T31	1		T178	3		T208	3
auto[1]	values[5]	values[3]	10	1			T22	4		T23	1		T184	4
auto[1]	values[5]	values[4]	10	1			T36	1		T179	3		T166	2
auto[1]	values[5]	values[5]	13	1			T31	2		T39	4		T146	1
auto[1]	values[5]	values[6]	11	1			T184	1		T165	4		T206	1
auto[1]	values[5]	values[7]	4	1			T225	1		T227	3		-	-
auto[1]	values[6]	values[0]	2	1			T228	2		-	-		-	-
auto[1]	values[6]	values[1]	4	1			T181	1		T206	1		T218	1
auto[1]	values[6]	values[2]	9	1			T30	2		T166	3		T226	2
auto[1]	values[6]	values[3]	5	1			T22	2		T37	1		T155	1
auto[1]	values[6]	values[5]	5	1			T22	1		T170	3		T201	1
auto[1]	values[6]	values[6]	6	1			T219	1		T229	1		T214	2
auto[1]	values[6]	values[7]	4	1			T31	3		T39	1		-	-
auto[1]	values[7]	values[0]	12	1			T144	2		T184	2		T230	3
auto[1]	values[7]	values[1]	10	1			T7	1		T164	2		T231	2
auto[1]	values[7]	values[2]	15	1			T7	1		T22	3		T39	1
auto[1]	values[7]	values[3]	8	1			T144	1		T165	2		T214	1
auto[1]	values[7]	values[4]	4	1			T31	2		T225	1		T232	1
auto[1]	values[7]	values[5]	7	1			T214	2		T166	2		T196	2
auto[1]	values[7]	values[6]	13	1			T22	1		T31	4		T39	1
auto[1]	values[7]	values[7]	5	1			T40	1		T178	3		T205	1