Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2769

1

T6

7

T7

6

T9

27

auto[1]

2799

1

T6

22

T7

3

T9

26

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3080

1

T6

29

T7

8

T10

24

auto[1]

2488

1

T7

1

T9

53

T10

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4337

1

T6

17

T7

6

T9

53

auto[1]

1231

1

T6

12

T7

3

T10

11

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1111	1			T6	4		T9	11		T10	3
valid[1]	1104	1			T6	4		T7	3		T9	12
valid[2]	1154	1			T6	7		T9	10		T10	9
valid[3]	1122	1			T6	9		T7	4		T9	10
valid[4]	1077	1			T6	5		T7	2		T9	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	187	1			T11	3		T67	1		T22	1
auto[0]	auto[0]	valid[0]	auto[1]	258	1			T9	4		T10	1		T19	3
auto[0]	auto[0]	valid[1]	auto[0]	181	1			T6	1		T7	2		T10	1
auto[0]	auto[0]	valid[1]	auto[1]	235	1			T9	9		T19	2		T20	1
auto[0]	auto[0]	valid[2]	auto[0]	189	1			T10	2		T18	2		T11	1
auto[0]	auto[0]	valid[2]	auto[1]	247	1			T9	3		T19	2		T20	2
auto[0]	auto[0]	valid[3]	auto[0]	174	1			T6	1		T7	1		T61	1
auto[0]	auto[0]	valid[3]	auto[1]	241	1			T9	6		T10	1		T19	1
auto[0]	auto[0]	valid[4]	auto[0]	188	1			T7	1		T10	2		T11	1
auto[0]	auto[0]	valid[4]	auto[1]	258	1			T9	5		T19	4		T20	2
auto[0]	auto[1]	valid[0]	auto[0]	180	1			T6	3		T10	1		T18	2
auto[0]	auto[1]	valid[0]	auto[1]	244	1			T9	7		T19	7		T20	3
auto[0]	auto[1]	valid[1]	auto[0]	189	1			T6	2		T18	1		T61	1
auto[0]	auto[1]	valid[1]	auto[1]	263	1			T9	3		T19	3		T20	1
auto[0]	auto[1]	valid[2]	auto[0]	201	1			T6	1		T10	2		T18	2
auto[0]	auto[1]	valid[2]	auto[1]	265	1			T9	7		T19	4		T20	1
auto[0]	auto[1]	valid[3]	auto[0]	194	1			T6	5		T10	2		T18	1
auto[0]	auto[1]	valid[3]	auto[1]	248	1			T7	1		T9	4		T19	4
auto[0]	auto[1]	valid[4]	auto[0]	166	1			T6	4		T7	1		T10	3
auto[0]	auto[1]	valid[4]	auto[1]	229	1			T9	5		T19	3		T65	5
auto[1]	auto[0]	valid[0]	auto[0]	121	1			T11	1		T61	2		T67	2
auto[1]	auto[0]	valid[1]	auto[0]	114	1			T7	1		T10	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	130	1			T6	4		T10	2		T61	2
auto[1]	auto[0]	valid[3]	auto[0]	129	1			T6	1		T7	1		T10	1
auto[1]	auto[0]	valid[4]	auto[0]	117	1			T10	2		T67	1		T30	1
auto[1]	auto[1]	valid[0]	auto[0]	121	1			T6	1		T10	1		T11	1
auto[1]	auto[1]	valid[1]	auto[0]	122	1			T6	1		T18	1		T31	1
auto[1]	auto[1]	valid[2]	auto[0]	122	1			T6	2		T10	3		T18	1
auto[1]	auto[1]	valid[3]	auto[0]	136	1			T6	2		T7	1		T11	2
auto[1]	auto[1]	valid[4]	auto[0]	119	1			T6	1		T10	1		T67	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal