Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77048

1

T1

16

T6

602

T7

147

auto[1]

24729

1

T7

20

T9

597

T10

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73843

1

T1

9

T6

392

T7

116

auto[1]

27934

1

T1

7

T6

210

T7

51

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	52392	1			T1	9		T6	310		T7	95
others[1]	8516	1			T1	2		T6	52		T7	10
others[2]	8613	1			T1	1		T6	56		T7	15
others[3]	9921	1			T6	62		T7	15		T9	51
interest[1]	5573	1			T1	1		T6	28		T7	12
interest[4]	34210	1			T1	4		T6	209		T7	61
interest[64]	16762	1			T1	3		T6	94		T7	20

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	25133	1			T1	4		T6	201		T7	60
auto[0]	auto[0]	others[1]	4140	1			T1	1		T6	35		T7	6
auto[0]	auto[0]	others[2]	4150	1			T1	1		T6	39		T7	7
auto[0]	auto[0]	others[3]	4780	1			T6	41		T7	10		T10	25
auto[0]	auto[0]	interest[1]	2726	1			T1	1		T6	14		T7	6
auto[0]	auto[0]	interest[4]	16337	1			T1	2		T6	132		T7	38
auto[0]	auto[0]	interest[64]	8185	1			T1	2		T6	62		T7	7
auto[0]	auto[1]	others[0]	13023	1			T7	12		T9	312		T10	24
auto[0]	auto[1]	others[1]	2016	1			T9	50		T10	2		T19	27
auto[0]	auto[1]	others[2]	2092	1			T7	3		T9	58		T10	2
auto[0]	auto[1]	others[3]	2342	1			T7	1		T9	51		T10	9
auto[0]	auto[1]	interest[1]	1341	1			T7	1		T9	34		T10	2
auto[0]	auto[1]	interest[4]	8701	1			T7	11		T9	198		T10	14
auto[0]	auto[1]	interest[64]	3915	1			T7	3		T9	92		T10	9
auto[1]	auto[0]	others[0]	14236	1			T1	5		T6	109		T7	23
auto[1]	auto[0]	others[1]	2360	1			T1	1		T6	17		T7	4
auto[1]	auto[0]	others[2]	2371	1			T6	17		T7	5		T10	14
auto[1]	auto[0]	others[3]	2799	1			T6	21		T7	4		T10	16
auto[1]	auto[0]	interest[1]	1506	1			T6	14		T7	5		T10	14
auto[1]	auto[0]	interest[4]	9172	1			T1	2		T6	77		T7	12
auto[1]	auto[0]	interest[64]	4662	1			T1	1		T6	32		T7	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal