Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	2	34	94.44

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	2	34	94.44	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	817	1			T22	17		T30	10		T31	11
all_values[1]	817	1			T22	17		T30	10		T31	11
all_values[2]	817	1			T22	17		T30	10		T31	11
all_values[3]	817	1			T22	17		T30	10		T31	11
all_values[4]	817	1			T22	17		T30	10		T31	11
all_values[5]	817	1			T22	17		T30	10		T31	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645

1

T22

50

T30

40

T31

43

auto[1]

2257

1

T22

52

T30

20

T31

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2021

1

T22

48

T30

26

T31

22

auto[1]

2881

1

T22

54

T30

34

T31

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2753

1

T22

61

T30

34

T31

34

auto[1]

2149

1

T22

41

T30

26

T31

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	2	34	94.44	2
Automatically Generated Cross Bins	36	2	34	94.44	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	160	1			T22	3		T30	2		T31	1
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T30	1		T31	4		T37	1
all_values[0]	auto[0]	auto[1]	auto[0]	107	1			T22	5		T30	1		T31	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T22	4		T31	1		T45	1
all_values[0]	auto[1]	auto[0]	auto[1]	211	1			T22	4		T30	4		T31	2
all_values[0]	auto[1]	auto[1]	auto[1]	176	1			T22	1		T30	2		T31	2
all_values[1]	auto[0]	auto[0]	auto[0]	180	1			T22	5		T30	5		T31	3
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T22	1		T30	2		T31	1
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T22	2		T45	2		T37	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T31	1		T45	1		T57	2
all_values[1]	auto[1]	auto[0]	auto[1]	185	1			T22	3		T30	3		T31	3
all_values[1]	auto[1]	auto[1]	auto[1]	171	1			T22	6		T31	3		T45	3
all_values[2]	auto[0]	auto[0]	auto[0]	158	1			T22	5		T30	2		T31	2
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T22	1		T30	2		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	157	1			T22	5		T31	3		T45	3
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T22	1		T31	1		T80	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T22	2		T30	4		T31	3
all_values[2]	auto[1]	auto[1]	auto[1]	152	1			T22	3		T30	2		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	191	1			T22	7		T30	1		T31	3
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T30	1		T57	1		T144	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T22	4		T30	5		T45	3
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T22	2		T30	1		T31	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T22	2		T30	1		T31	4
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T22	2		T30	1		T31	3
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T22	2		T30	2		T31	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T22	1		T30	1		T31	2
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T22	1		T30	2		T45	2
all_values[4]	auto[0]	auto[1]	auto[1]	63	1			T22	3		T45	1		T144	2
all_values[4]	auto[1]	auto[0]	auto[1]	195	1			T22	4		T30	4		T31	6
all_values[4]	auto[1]	auto[1]	auto[1]	173	1			T22	6		T30	1		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	249	1			T22	5		T30	3		T31	5
all_values[5]	auto[0]	auto[1]	auto[0]	236	1			T22	4		T30	3		T31	3
all_values[5]	auto[1]	auto[0]	auto[1]	184	1			T22	5		T30	2		T31	2
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T22	3		T30	2		T31	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal