Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	8120668	1			T1	3818		T2	1		T3	6057
all_values[1]	8120668	1			T1	3818		T2	1		T3	6057
all_values[2]	8120668	1			T1	3818		T2	1		T3	6057
all_values[3]	8120668	1			T1	3818		T2	1		T3	6057
all_values[4]	8120668	1			T1	3818		T2	1		T3	6057
all_values[5]	8120668	1			T1	3818		T2	1		T3	6057

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46321381

1

T1

22908

T2

6

T3

36342

auto[1]

2402627

1

T11

427898

T27

54359

T29

32263

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48642704

1

T1

22087

T2

6

T3

36023

auto[1]

81304

1

T1

821

T3

319

T11

575

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7702977	1			T1	3278		T2	1		T3	5901
all_values[0]	auto[0]	auto[1]	45589	1			T1	540		T3	156		T11	344
all_values[0]	auto[1]	auto[0]	369663	1			T11	11		T27	4		T29	31609
all_values[0]	auto[1]	auto[1]	2439	1			T11	7		T27	3		T29	633
all_values[1]	auto[0]	auto[0]	7892100	1			T1	3574		T2	1		T3	5955
all_values[1]	auto[0]	auto[1]	22809	1			T1	244		T3	102		T11	141
all_values[1]	auto[1]	auto[0]	205194	1			T11	7		T27	17936		T29	3
all_values[1]	auto[1]	auto[1]	565	1			T11	7		T27	180		T29	2
all_values[2]	auto[0]	auto[0]	7489752	1			T1	3781		T2	1		T3	5996
all_values[2]	auto[0]	auto[1]	7848	1			T1	37		T3	61		T11	10
all_values[2]	auto[1]	auto[0]	622324	1			T11	213888		T27	18005		T32	4
all_values[2]	auto[1]	auto[1]	744	1			T11	27		T27	114		T29	3
all_values[3]	auto[0]	auto[0]	7647253	1			T1	3818		T2	1		T3	6057
all_values[3]	auto[0]	auto[1]	214	1			T11	8		T27	1		T29	4
all_values[3]	auto[1]	auto[0]	473042	1			T11	10		T27	18112		T29	3
all_values[3]	auto[1]	auto[1]	159	1			T11	3		T27	3		T29	1
all_values[4]	auto[0]	auto[0]	7906507	1			T1	3818		T2	1		T3	6057
all_values[4]	auto[0]	auto[1]	181	1			T11	7		T39	1		T27	1
all_values[4]	auto[1]	auto[0]	213793	1			T11	11		T27	1		T29	3
all_values[4]	auto[1]	auto[1]	187	1			T11	10		T29	1		T32	4
all_values[5]	auto[0]	auto[0]	7605740	1			T1	3818		T2	1		T3	6057
all_values[5]	auto[0]	auto[1]	411	1			T11	4		T27	4		T29	2
all_values[5]	auto[1]	auto[0]	514359	1			T11	213910		T27	1		T29	2
all_values[5]	auto[1]	auto[1]	158	1			T11	7		T29	3		T32	1