Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	44051	1			T1	730		T3	303		T5	8
auto[SpiFlashAddrCfg]	9735	1			T1	56		T3	29		T5	10
auto[SpiFlashAddr3b]	11510	1			T1	52		T3	62		T5	4
auto[SpiFlashAddr4b]	9962	1			T1	65		T3	58		T5	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42422

1

T1

421

T3

305

T5

24

auto[1]

32836

1

T1

482

T3

147

T11

224

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40048

1

T1

507

T3

196

T5

14

auto[1]

35210

1

T1

396

T3

256

T5

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	49861	1			T1	776		T3	332		T5	12
values[1]	1437	1			T1	5		T3	4		T11	19
values[2]	1894	1			T1	2		T3	7		T5	2
values[3]	1904	1			T1	13		T3	9		T5	4
values[4]	1851	1			T1	8		T3	10		T11	25
values[5]	1814	1			T1	12		T3	6		T7	2
values[6]	1940	1			T1	6		T3	18		T11	17
values[7]	1835	1			T1	15		T3	12		T11	14
values[8]	12722	1			T1	66		T3	54		T5	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35044

1

T5

24

T7

16

T8

14

auto[1]

40214

1

T1

903

T3

452

T23

213

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

72528

1

T1

880

T3

432

T5

24

write

2730

1

T1

23

T3

20

T11

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

25386

1

T1

146

T3

119

T5

18

valids[0x1]

49872

1

T1

757

T3

333

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	2021	1			T1	10		T3	10		T5	2
internal_process_ops[0x5a]	1952	1			T1	5		T3	6		T7	2
internal_process_ops[0x05]	26233	1			T1	631		T3	220		T9	2
internal_process_ops[0x35]	2095	1			T1	9		T3	14		T7	4
internal_process_ops[0x15]	2043	1			T1	9		T3	15		T7	2
internal_process_ops[0x03]	1330	1			T1	4		T11	22		T23	1
internal_process_ops[0x0b]	1373	1			T1	7		T3	1		T5	4
internal_process_ops[0x3b]	1396	1			T1	8		T3	6		T7	2
internal_process_ops[0x6b]	1423	1			T1	8		T3	5		T12	2
internal_process_ops[0xbb]	1292	1			T1	5		T3	1		T5	4
internal_process_ops[0xeb]	1498	1			T1	9		T3	8		T5	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73875

1

T1

893

T3

437

T5

24

auto[1]

1383

1

T1

10

T3

15

T11

15

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72555

1

T1

879

T3

435

T5

24

auto[1]

2703

1

T1

24

T3

17

T11

17

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11332

1

T5

8

T7

12

T8

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7362

1

T11

57

T25

40

T26

173

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2603

1

T5

10

T7

2

T8

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2155

1

T11

38

T25

22

T26

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2968

1

T5

4

T7

2

T8

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2662

1

T11

67

T25

21

T26

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2532

1

T5

2

T12

16

T11

51

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2197

1

T11

53

T25

26

T26

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T11

3

T24

2

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T11

3

T29

2

T31

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T11

1

T25

1

T29

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T11

1

T25

4

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

84

1

T11

1

T139

4

T140

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T11

2

T25

1

T29

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

55

1

T11

2

T30

1

T71

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T11

3

T25

2

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

71

1

T11

1

T25

2

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T11

3

T26

1

T29

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

69

1

T25

3

T26

3

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

87

1

T25

1

T26

1

T29

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

76

1

T29

5

T33

3

T34

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T11

2

T25

1

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

64

1

T11

1

T29

5

T31

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T11

1

T26

3

T29

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

14302

1

T1

339

T3

227

T23

24

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

10333

1

T1

385

T3

69

T23

139

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2289

1

T1

27

T3

17

T23

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2011

1

T1

20

T3

9

T23

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2687

1

T1

15

T3

26

T23

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2531

1

T1

33

T3

31

T23

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2356

1

T1

25

T3

23

T23

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2208

1

T1

36

T3

30

T23

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T1

1

T27

4

T120

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T1

4

T3

6

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T3

1

T28

3

T120

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T1

1

T27

3

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T1

5

T27

1

T106

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T106

3

T141

2

T142

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T1

3

T3

3

T22

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T1

1

T22

2

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

73

1

T1

2

T22

3

T69

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T3

2

T22

1

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

95

1

T1

1

T27

2

T143

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T1

1

T3

3

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

78

1

T1

1

T3

1

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

94

1

T1

2

T3

3

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

107

1

T23

1

T22

2

T28

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T1

1

T3

1

T22

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4609	1			T5	6		T7	2		T12	6
auto[0]	values[0]	valids[0x1]	17182	1			T5	6		T7	8		T8	6
auto[0]	values[1]	valids[0x1]	709	1			T11	19		T25	9		T79	4
auto[0]	values[2]	valids[0x0]	675	1			T5	2		T7	2		T8	4
auto[0]	values[2]	valids[0x1]	339	1			T11	9		T25	2		T26	2
auto[0]	values[3]	valids[0x0]	634	1			T5	4		T11	8		T25	13
auto[0]	values[3]	valids[0x1]	355	1			T8	2		T11	4		T25	5
auto[0]	values[4]	valids[0x0]	718	1			T11	18		T36	4		T25	5
auto[0]	values[4]	valids[0x1]	312	1			T11	7		T25	2		T29	15
auto[0]	values[5]	valids[0x0]	616	1			T12	2		T11	7		T37	2
auto[0]	values[5]	valids[0x1]	328	1			T7	2		T9	2		T11	6
auto[0]	values[6]	valids[0x0]	650	1			T11	7		T25	3		T26	3
auto[0]	values[6]	valids[0x1]	356	1			T11	10		T37	2		T25	5
auto[0]	values[7]	valids[0x0]	603	1			T11	3		T25	3		T26	1
auto[0]	values[7]	valids[0x1]	389	1			T11	11		T25	2		T79	2
auto[0]	values[8]	valids[0x0]	4144	1			T5	6		T12	8		T11	91
auto[0]	values[8]	valids[0x1]	2425	1			T7	2		T8	2		T11	38
auto[1]	values[0]	valids[0x0]	5904	1			T1	70		T3	44		T23	27
auto[1]	values[0]	valids[0x1]	22166	1			T1	706		T3	288		T23	146
auto[1]	values[1]	valids[0x1]	728	1			T1	5		T3	4		T23	2
auto[1]	values[2]	valids[0x0]	534	1			T3	6		T23	1		T22	7
auto[1]	values[2]	valids[0x1]	346	1			T1	2		T3	1		T23	2
auto[1]	values[3]	valids[0x0]	557	1			T1	11		T3	8		T23	2
auto[1]	values[3]	valids[0x1]	358	1			T1	2		T3	1		T22	1
auto[1]	values[4]	valids[0x0]	498	1			T1	5		T3	2		T23	1
auto[1]	values[4]	valids[0x1]	323	1			T1	3		T3	8		T22	4
auto[1]	values[5]	valids[0x0]	516	1			T1	8		T3	4		T23	6
auto[1]	values[5]	valids[0x1]	354	1			T1	4		T3	2		T23	1
auto[1]	values[6]	valids[0x0]	575	1			T1	4		T3	9		T23	1
auto[1]	values[6]	valids[0x1]	359	1			T1	2		T3	9		T22	6
auto[1]	values[7]	valids[0x0]	500	1			T1	9		T3	6		T23	3
auto[1]	values[7]	valids[0x1]	343	1			T1	6		T3	6		T22	8
auto[1]	values[8]	valids[0x0]	3653	1			T1	39		T3	40		T23	10
auto[1]	values[8]	valids[0x1]	2500	1			T1	27		T3	14		T23	11