Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20630

1

T1

118

T3

89

T4

9

auto[1]

26615

1

T1

647

T3

228

T11

115

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17272

1

T1

116

T3

68

T4

9

auto[1]

29973

1

T1

649

T3

249

T7

6

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7687	1			T1	9		T3	23		T4	2
auto[524288:1048575]	6193	1			T1	36		T3	122		T10	1
auto[1048576:1572863]	6065	1			T1	267		T3	20		T11	46
auto[1572864:2097151]	5482	1			T1	69		T3	107		T11	50
auto[2097152:2621439]	4910	1			T1	86		T3	7		T4	7
auto[2621440:3145727]	5545	1			T1	11		T3	19		T11	11
auto[3145728:3670015]	5235	1			T1	1		T3	2		T11	19
auto[3670016:4194303]	6128	1			T1	286		T3	17		T11	12

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46154

1

T1

758

T3

309

T4

9

auto[1]

1091

1

T1

7

T3

8

T11

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37580

1

T1

587

T3

245

T4

9

auto[1]

9665

1

T1

178

T3

72

T11

35

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	2104	1			T1	4		T3	11		T4	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	938	1			T1	1		T3	9		T7	6
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1477	1			T1	5		T3	4		T10	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	615	1			T1	2		T3	5		T11	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1400	1			T1	28		T3	4		T11	14
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	567	1			T1	7		T3	3		T11	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1273	1			T1	5		T3	12		T11	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	490	1			T1	1		T3	7		T11	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1274	1			T1	6		T3	5		T4	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	493	1			T1	1		T3	2		T11	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1484	1			T1	3		T3	4		T11	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	550	1			T1	3		T3	1		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1336	1			T1	1		T3	1		T11	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	553	1			T3	1		T11	6		T22	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1412	1			T1	13		T3	6		T11	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	567	1			T1	2		T3	6		T11	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	359	1			T1	3		T3	1		T11	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	157	1			T1	1		T3	2		T11	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	298	1			T1	6		T3	2		T11	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	120	1			T1	4		T22	1		T25	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	347	1			T1	5		T11	5		T22	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	181	1			T1	1		T25	1		T27	9
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	353	1			T1	6		T23	1		T22	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	169	1			T1	2		T3	1		T22	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	368	1			T1	1		T11	5		T38	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	169	1			T1	1		T11	3		T22	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	333	1			T3	1		T11	3		T22	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	143	1			T3	1		T11	2		T22	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	340	1			T11	1		T22	5		T27	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	160	1			T22	3		T27	4		T28	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	411	1			T1	6		T25	2		T26	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	189	1			T11	1		T26	5		T29	6
auto[1]	auto[0]	auto[0:524287]	auto[0]	348	1			T11	4		T23	3		T22	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3062	1			T11	19		T23	13		T22	79
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	306	1			T3	3		T11	1		T22	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2839	1			T3	52		T11	20		T22	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	278	1			T1	9		T3	2		T11	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2623	1			T1	217		T3	11		T11	17
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	239	1			T1	2		T3	7		T11	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1948	1			T1	53		T3	80		T11	32
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	219	1			T1	3		T11	2		T22	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1812	1			T1	74		T11	4		T22	32
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	293	1			T1	1		T3	1		T22	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2179	1			T1	4		T3	3		T22	77
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	242	1			T11	1		T22	1		T25	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2082	1			T11	4		T22	3		T25	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	247	1			T1	4		T3	2		T22	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2330	1			T1	138		T3	3		T22	13
auto[1]	auto[1]	auto[0:524287]	auto[0]	70	1			T11	2		T23	1		T120	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	649	1			T11	2		T23	47		T120	12
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	50	1			T1	2		T3	1		T22	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	488	1			T1	17		T3	55		T22	16
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	79	1			T27	2		T29	2		T120	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	590	1			T27	5		T29	3		T120	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	71	1			T27	1		T29	3		T120	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	939	1			T27	16		T29	65		T120	38
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	65	1			T25	3		T26	1		T29	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	510	1			T25	16		T26	31		T29	10
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	58	1			T3	1		T26	2		T69	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	505	1			T3	7		T26	24		T69	10
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	58	1			T22	1		T27	3		T28	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	464	1			T22	44		T27	7		T28	33
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	80	1			T1	3		T25	1		T28	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	892	1			T1	120		T25	1		T28	34

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	16082	1			T1	78		T3	74		T4	9
auto[0]	auto[0]	auto[1]	451	1			T1	4		T3	7		T11	3
auto[0]	auto[1]	auto[0]	3973	1			T1	33		T3	8		T11	31
auto[0]	auto[1]	auto[1]	124	1			T1	3		T23	1		T22	1
auto[1]	auto[0]	auto[0]	20629	1			T1	505		T3	163		T11	109
auto[1]	auto[0]	auto[1]	418	1			T3	1		T11	2		T23	2
auto[1]	auto[1]	auto[0]	5470	1			T1	142		T3	64		T11	4
auto[1]	auto[1]	auto[1]	98	1			T28	3		T29	2		T31	1