Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20067

1

T5

24

T7

16

T8

14

auto[1]

14977

1

T11

224

T25

120

T26

213

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4644	1			T5	24		T7	16		T12	26
values[1]	4224	1			T8	14		T11	20		T37	22
values[2]	3933	1			T11	114		T25	22		T26	44
values[3]	4649	1			T10	2		T11	56		T25	60
values[4]	4876	1			T9	6		T11	86		T25	44
values[5]	3837	1			T11	76		T29	51		T31	99
values[6]	4264	1			T11	40		T36	16		T26	71
values[7]	4617	1			T11	65		T38	4		T25	103

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3812	1			T7	16		T11	24		T24	41
values[1]	4343	1			T11	93		T29	170		T119	28
values[2]	4613	1			T10	2		T12	26		T11	107
values[3]	4462	1			T11	59		T36	16		T25	104
values[4]	4263	1			T5	24		T11	45		T25	40
values[5]	4431	1			T9	6		T11	60		T37	22
values[6]	4780	1			T8	14		T11	150		T38	4
values[7]	4340	1			T11	20		T25	24		T26	93

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	252	1			T7	16		T24	41		T139	30
auto[0]	values[0]	values[1]	235	1			T32	9		T173	15		T179	21
auto[0]	values[0]	values[2]	261	1			T12	26		T11	32		T151	22
auto[0]	values[0]	values[3]	366	1			T30	16		T31	11		T71	10
auto[0]	values[0]	values[4]	321	1			T5	24		T25	12		T32	11
auto[0]	values[0]	values[5]	311	1			T11	4		T66	13		T58	10
auto[0]	values[0]	values[6]	537	1			T11	23		T29	114		T236	8
auto[0]	values[0]	values[7]	210	1			T58	11		T237	13		T177	9
auto[0]	values[1]	values[0]	351	1			T238	4		T167	12		T58	60
auto[0]	values[1]	values[1]	171	1			T29	11		T33	8		T185	7
auto[0]	values[1]	values[2]	510	1			T25	104		T29	11		T151	10
auto[0]	values[1]	values[3]	200	1			T25	11		T29	13		T239	4
auto[0]	values[1]	values[4]	196	1			T25	14		T34	27		T58	29
auto[0]	values[1]	values[5]	284	1			T37	22		T151	13		T32	9
auto[0]	values[1]	values[6]	403	1			T8	14		T29	20		T33	45
auto[0]	values[1]	values[7]	363	1			T11	10		T26	16		T29	49
auto[0]	values[2]	values[0]	268	1			T240	8		T58	13		T163	12
auto[0]	values[2]	values[1]	400	1			T29	8		T119	28		T58	11
auto[0]	values[2]	values[2]	357	1			T11	14		T33	48		T171	16
auto[0]	values[2]	values[3]	279	1			T29	11		T30	17		T31	42
auto[0]	values[2]	values[4]	173	1			T11	13		T29	12		T31	10
auto[0]	values[2]	values[5]	380	1			T25	10		T241	12		T58	12
auto[0]	values[2]	values[6]	371	1			T11	44		T26	35		T29	10
auto[0]	values[2]	values[7]	246	1			T29	12		T31	76		T151	17
auto[0]	values[3]	values[0]	379	1			T25	7		T118	95		T154	7
auto[0]	values[3]	values[1]	471	1			T11	17		T29	11		T172	4
auto[0]	values[3]	values[2]	368	1			T10	2		T29	9		T34	86
auto[0]	values[3]	values[3]	297	1			T25	20		T31	10		T162	4
auto[0]	values[3]	values[4]	239	1			T29	14		T225	8		T191	8
auto[0]	values[3]	values[5]	281	1			T29	31		T66	11		T169	20
auto[0]	values[3]	values[6]	292	1			T11	23		T32	14		T33	11
auto[0]	values[3]	values[7]	310	1			T31	20		T242	10		T32	12
auto[0]	values[4]	values[0]	265	1			T31	31		T33	12		T243	6
auto[0]	values[4]	values[1]	393	1			T11	7		T29	26		T30	7
auto[0]	values[4]	values[2]	390	1			T11	12		T29	8		T159	13
auto[0]	values[4]	values[3]	294	1			T11	32		T25	25		T31	6
auto[0]	values[4]	values[4]	518	1			T29	101		T30	11		T32	13
auto[0]	values[4]	values[5]	252	1			T9	6		T29	22		T30	13
auto[0]	values[4]	values[6]	338	1			T32	15		T33	6		T170	9
auto[0]	values[4]	values[7]	250	1			T29	15		T31	19		T107	10
auto[0]	values[5]	values[0]	290	1			T11	12		T58	16		T219	14
auto[0]	values[5]	values[1]	235	1			T11	24		T31	11		T157	2
auto[0]	values[5]	values[2]	287	1			T11	9		T31	25		T32	17
auto[0]	values[5]	values[3]	230	1			T32	10		T154	9		T241	14
auto[0]	values[5]	values[4]	217	1			T29	34		T244	12		T245	10
auto[0]	values[5]	values[5]	375	1			T31	13		T107	51		T58	14
auto[0]	values[5]	values[6]	296	1			T246	2		T146	16		T152	22
auto[0]	values[5]	values[7]	320	1			T151	13		T247	12		T159	26
auto[0]	values[6]	values[0]	267	1			T154	16		T58	15		T144	14
auto[0]	values[6]	values[1]	384	1			T32	16		T248	42		T58	45
auto[0]	values[6]	values[2]	231	1			T29	75		T151	12		T107	9
auto[0]	values[6]	values[3]	408	1			T11	11		T36	16		T29	54
auto[0]	values[6]	values[4]	204	1			T33	12		T58	12		T249	2
auto[0]	values[6]	values[5]	202	1			T11	11		T216	10		T179	9
auto[0]	values[6]	values[6]	423	1			T26	21		T29	105		T140	22
auto[0]	values[6]	values[7]	356	1			T31	19		T58	11		T237	15
auto[0]	values[7]	values[0]	460	1			T25	12		T29	21		T31	100
auto[0]	values[7]	values[1]	247	1			T11	13		T29	10		T30	8
auto[0]	values[7]	values[2]	221	1			T25	55		T179	12		T220	23
auto[0]	values[7]	values[3]	276	1			T156	6		T159	12		T58	10
auto[0]	values[7]	values[4]	316	1			T11	12		T71	9		T150	14
auto[0]	values[7]	values[5]	458	1			T11	11		T79	22		T26	11
auto[0]	values[7]	values[6]	245	1			T38	4		T26	8		T32	32
auto[0]	values[7]	values[7]	337	1			T25	12		T107	12		T171	14
auto[1]	values[0]	values[0]	68	1			T163	7		T152	8		T183	10
auto[1]	values[0]	values[1]	180	1			T32	11		T173	5		T179	8
auto[1]	values[0]	values[2]	270	1			T11	8		T151	18		T146	7
auto[1]	values[0]	values[3]	220	1			T30	6		T31	35		T71	10
auto[1]	values[0]	values[4]	436	1			T25	8		T32	11		T171	10
auto[1]	values[0]	values[5]	370	1			T11	16		T66	9		T165	26
auto[1]	values[0]	values[6]	366	1			T11	18		T29	29		T199	16
auto[1]	values[0]	values[7]	241	1			T58	10		T237	7		T177	11
auto[1]	values[1]	values[0]	148	1			T58	14		T177	9		T179	5
auto[1]	values[1]	values[1]	110	1			T29	10		T33	12		T250	2
auto[1]	values[1]	values[2]	331	1			T25	9		T29	34		T151	15
auto[1]	values[1]	values[3]	210	1			T25	9		T29	11		T146	31
auto[1]	values[1]	values[4]	213	1			T25	6		T34	9		T58	15
auto[1]	values[1]	values[5]	204	1			T151	7		T32	11		T66	10
auto[1]	values[1]	values[6]	243	1			T29	28		T33	7		T34	39
auto[1]	values[1]	values[7]	287	1			T11	10		T26	77		T29	35
auto[1]	values[2]	values[0]	109	1			T58	8		T163	11		T173	11
auto[1]	values[2]	values[1]	224	1			T29	12		T58	9		T146	4
auto[1]	values[2]	values[2]	204	1			T11	7		T33	7		T171	4
auto[1]	values[2]	values[3]	167	1			T29	16		T30	3		T31	9
auto[1]	values[2]	values[4]	163	1			T11	7		T29	8		T31	10
auto[1]	values[2]	values[5]	149	1			T25	12		T241	8		T58	8
auto[1]	values[2]	values[6]	309	1			T11	29		T26	9		T29	22
auto[1]	values[2]	values[7]	134	1			T29	8		T31	19		T151	4
auto[1]	values[3]	values[0]	176	1			T25	13		T154	13		T146	5
auto[1]	values[3]	values[1]	235	1			T11	3		T29	9		T33	8
auto[1]	values[3]	values[2]	277	1			T29	65		T34	4		T154	15
auto[1]	values[3]	values[3]	368	1			T25	20		T31	10		T58	8
auto[1]	values[3]	values[4]	324	1			T29	6		T191	12		T216	45
auto[1]	values[3]	values[5]	245	1			T29	17		T66	12		T144	9
auto[1]	values[3]	values[6]	196	1			T11	13		T32	6		T33	9
auto[1]	values[3]	values[7]	191	1			T31	3		T32	19		T150	6
auto[1]	values[4]	values[0]	115	1			T31	12		T33	10		T171	13
auto[1]	values[4]	values[1]	502	1			T11	14		T29	26		T30	20
auto[1]	values[4]	values[2]	182	1			T11	14		T29	13		T159	16
auto[1]	values[4]	values[3]	433	1			T11	7		T25	19		T31	64
auto[1]	values[4]	values[4]	299	1			T29	4		T30	9		T32	7
auto[1]	values[4]	values[5]	250	1			T29	22		T30	7		T71	26
auto[1]	values[4]	values[6]	128	1			T32	5		T33	14		T170	11
auto[1]	values[4]	values[7]	267	1			T29	11		T31	99		T107	10
auto[1]	values[5]	values[0]	281	1			T11	12		T145	2		T58	26
auto[1]	values[5]	values[1]	192	1			T11	8		T31	9		T58	9
auto[1]	values[5]	values[2]	221	1			T11	11		T31	34		T32	7
auto[1]	values[5]	values[3]	215	1			T32	11		T175	2		T154	11
auto[1]	values[5]	values[4]	123	1			T29	17		T58	8		T150	7
auto[1]	values[5]	values[5]	134	1			T31	7		T107	18		T58	7
auto[1]	values[5]	values[6]	109	1			T146	4		T152	21		T216	7
auto[1]	values[5]	values[7]	312	1			T151	7		T159	4		T173	9
auto[1]	values[6]	values[0]	196	1			T154	4		T58	5		T144	6
auto[1]	values[6]	values[1]	110	1			T32	4		T58	7		T177	20
auto[1]	values[6]	values[2]	192	1			T29	12		T151	23		T107	11
auto[1]	values[6]	values[3]	248	1			T11	9		T29	24		T32	16
auto[1]	values[6]	values[4]	214	1			T33	8		T58	8		T150	12
auto[1]	values[6]	values[5]	267	1			T11	9		T160	34		T216	10
auto[1]	values[6]	values[6]	339	1			T26	50		T29	24		T33	34
auto[1]	values[6]	values[7]	223	1			T31	53		T58	9		T237	8
auto[1]	values[7]	values[0]	187	1			T25	8		T29	3		T31	6
auto[1]	values[7]	values[1]	254	1			T11	7		T29	47		T30	12
auto[1]	values[7]	values[2]	311	1			T25	4		T179	14		T220	28
auto[1]	values[7]	values[3]	251	1			T35	28		T159	8		T58	10
auto[1]	values[7]	values[4]	307	1			T11	13		T71	16		T150	6
auto[1]	values[7]	values[5]	269	1			T11	9		T26	65		T29	23
auto[1]	values[7]	values[6]	185	1			T26	12		T32	39		T33	8
auto[1]	values[7]	values[7]	293	1			T25	12		T107	17		T171	6