Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	431	1			T11	6		T26	2		T29	15
auto[ReadAddrCrossIntoMailbox]	356	1			T11	8		T25	2		T26	1
auto[ReadAddrCrossOutOfMailbox]	379	1			T11	10		T25	1		T26	2
auto[ReadAddrCrossAllMailbox]	238	1			T11	4		T25	1		T26	1
auto[ReadAddrOutsideMailbox]	4319	1			T5	10		T7	2		T12	18

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2873

1

T5

5

T7

1

T12

9

auto[1]

2850

1

T5

5

T7

1

T12

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	908	1			T11	22		T37	4		T25	10
read_ops[0x0b]	983	1			T5	4		T12	8		T11	20
read_ops[0x3b]	978	1			T7	2		T12	4		T11	18
read_ops[0x6b]	968	1			T12	2		T11	14		T25	11
read_ops[0xbb]	855	1			T5	4		T12	4		T11	15
read_ops[0xeb]	1031	1			T5	2		T11	17		T25	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T29	3		T151	1		T32	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T29	2		T34	1		T107	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T11	2		T29	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T11	1		T29	2		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T11	1		T29	2		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	1		T26	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T11	2		T29	2		T159	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T11	1		T29	1		T31	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T11	8		T37	2		T25	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	350	1			T11	6		T37	2		T25	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T29	1		T244	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T26	1		T29	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T11	1		T29	2		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T71	1		T33	1		T159	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T11	1		T29	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T159	1		T58	1		T144	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T11	1		T31	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T26	1		T32	1		T34	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	366	1			T5	2		T12	4		T11	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	383	1			T5	2		T12	4		T11	13
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T29	1		T244	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T29	2		T31	2		T244	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	41	1			T25	1		T29	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T11	1		T25	1		T29	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T11	1		T31	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T11	1		T25	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T25	1		T159	1		T146	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T29	1		T33	1		T241	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	373	1			T7	1		T12	2		T11	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	353	1			T7	1		T12	2		T11	8
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T11	3		T29	1		T33	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T26	1		T29	1		T31	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T71	1		T237	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T29	2		T107	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T71	1		T33	1		T66	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T11	2		T26	1		T29	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T30	1		T33	1		T58	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T29	1		T58	1		T150	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	358	1			T12	1		T11	2		T25	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	393	1			T12	1		T11	7		T25	8
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T11	1		T29	3		T30	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T11	1		T151	1		T161	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T11	1		T29	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T11	1		T151	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T29	2		T30	2		T107	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T11	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T29	3		T163	1		T173	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T171	1		T154	1		T58	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T5	2		T12	2		T11	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T5	2		T12	2		T11	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T11	1		T30	1		T71	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T32	2		T240	1		T231	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T11	1		T32	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T26	1		T29	1		T31	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	41	1			T31	2		T151	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T11	2		T151	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T31	1		T32	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T29	1		T154	2		T58	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	389	1			T5	1		T11	7		T25	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	385	1			T5	1		T11	6		T25	4