Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	8120668	1			T1	3818		T2	1		T3	6057
all_pins[1]	8120668	1			T1	3818		T2	1		T3	6057
all_pins[2]	8120668	1			T1	3818		T2	1		T3	6057
all_pins[3]	8120668	1			T1	3818		T2	1		T3	6057
all_pins[4]	8120668	1			T1	3818		T2	1		T3	6057
all_pins[5]	8120668	1			T1	3818		T2	1		T3	6057

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48712825	1			T1	22908		T2	6		T3	36342
values[0x1]	11183	1			T11	1558		T27	319		T29	689
transitions[0x0=>0x1]	10392	1			T11	1551		T27	197		T29	688
transitions[0x1=>0x0]	10406	1			T11	1551		T27	197		T29	688

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	8118118	1			T1	3818		T2	1		T3	6057
all_pins[0]	values[0x1]	2550	1			T11	7		T27	3		T29	679
all_pins[0]	transitions[0x0=>0x1]	2410	1			T11	5		T27	3		T29	679
all_pins[0]	transitions[0x1=>0x0]	448	1			T11	5		T27	193		T29	2
all_pins[1]	values[0x0]	8120080	1			T1	3818		T2	1		T3	6057
all_pins[1]	values[0x1]	588	1			T11	7		T27	193		T29	2
all_pins[1]	transitions[0x0=>0x1]	338	1			T11	7		T27	73		T29	2
all_pins[1]	transitions[0x1=>0x0]	527	1			T11	30		T29	3		T32	1
all_pins[2]	values[0x0]	8119891	1			T1	3818		T2	1		T3	6057
all_pins[2]	values[0x1]	777	1			T11	30		T27	120		T29	3
all_pins[2]	transitions[0x0=>0x1]	740	1			T11	30		T27	118		T29	2
all_pins[2]	transitions[0x1=>0x0]	122	1			T11	3		T27	1		T32	2
all_pins[3]	values[0x0]	8120509	1			T1	3818		T2	1		T3	6057
all_pins[3]	values[0x1]	159	1			T11	3		T27	3		T29	1
all_pins[3]	transitions[0x0=>0x1]	128	1			T11	2		T27	3		T29	1
all_pins[3]	transitions[0x1=>0x0]	156	1			T11	9		T29	1		T32	3
all_pins[4]	values[0x0]	8120481	1			T1	3818		T2	1		T3	6057
all_pins[4]	values[0x1]	187	1			T11	10		T29	1		T32	4
all_pins[4]	transitions[0x0=>0x1]	148	1			T11	7		T29	1		T32	4
all_pins[4]	transitions[0x1=>0x0]	6883	1			T11	1498		T29	3		T32	1
all_pins[5]	values[0x0]	8113746	1			T1	3818		T2	1		T3	6057
all_pins[5]	values[0x1]	6922	1			T11	1501		T29	3		T32	1
all_pins[5]	transitions[0x0=>0x1]	6628	1			T11	1500		T29	3		T32	1
all_pins[5]	transitions[0x1=>0x0]	2270	1			T11	6		T27	3		T29	679