Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4727	1			T10	2		T11	124		T24	41
values[1]	4262	1			T11	41		T25	20		T79	22
values[2]	4406	1			T12	26		T11	100		T25	81
values[3]	4092	1			T5	24		T11	56		T25	24
values[4]	4862	1			T11	106		T36	16		T25	40
values[5]	4445	1			T11	59		T29	91		T31	175
values[6]	4380	1			T7	16		T8	14		T11	52
values[7]	3870	1			T9	6		T11	20		T25	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5117	1			T11	60		T24	41		T38	4
values[1]	4561	1			T11	41		T25	24		T26	93
values[2]	4422	1			T5	24		T8	14		T9	6
values[3]	4281	1			T10	2		T11	198		T25	40
values[4]	4322	1			T11	82		T36	16		T25	20
values[5]	4136	1			T12	26		T25	40		T29	259
values[6]	4643	1			T7	16		T11	40		T25	40
values[7]	3562	1			T11	97		T37	22		T25	83

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34416

1

T5

24

T7

16

T8

14

auto[1]

628

1

T11

15

T25

9

T26

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	[values[5]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	570	1			T11	60		T24	41		T29	20
auto[0]	values[0]	values[1]	689	1			T11	20		T29	24		T32	20
auto[0]	values[0]	values[2]	465	1			T30	22		T31	20		T34	50
auto[0]	values[0]	values[3]	447	1			T10	2		T25	20		T32	26
auto[0]	values[0]	values[4]	496	1			T25	20		T58	50		T144	20
auto[0]	values[0]	values[5]	696	1			T33	22		T53	16		T58	84
auto[0]	values[0]	values[6]	739	1			T145	2		T146	61		T147	30
auto[0]	values[0]	values[7]	541	1			T11	44		T37	22		T71	20
auto[0]	values[1]	values[0]	592	1			T25	20		T148	24		T144	20
auto[0]	values[1]	values[1]	402	1			T29	19		T30	20		T33	20
auto[0]	values[1]	values[2]	414	1			T26	19		T30	27		T31	27
auto[0]	values[1]	values[3]	380	1			T33	19		T149	2		T150	20
auto[0]	values[1]	values[4]	820	1			T11	18		T29	43		T31	204
auto[0]	values[1]	values[5]	641	1			T29	173		T32	46		T33	20
auto[0]	values[1]	values[6]	581	1			T11	20		T26	75		T29	41
auto[0]	values[1]	values[7]	367	1			T79	22		T29	32		T107	29
auto[0]	values[2]	values[0]	726	1			T25	22		T29	86		T119	28
auto[0]	values[2]	values[1]	464	1			T11	20		T31	17		T151	20
auto[0]	values[2]	values[2]	583	1			T11	19		T29	26		T31	20
auto[0]	values[2]	values[3]	504	1			T11	21		T29	28		T152	18
auto[0]	values[2]	values[4]	399	1			T153	10		T154	41		T155	20
auto[0]	values[2]	values[5]	405	1			T12	26		T58	41		T146	40
auto[0]	values[2]	values[6]	771	1			T118	95		T34	69		T156	6
auto[0]	values[2]	values[7]	465	1			T11	32		T25	59		T71	35
auto[0]	values[3]	values[0]	570	1			T29	25		T151	25		T157	2
auto[0]	values[3]	values[1]	601	1			T25	24		T107	20		T158	14
auto[0]	values[3]	values[2]	522	1			T5	24		T29	101		T151	20
auto[0]	values[3]	values[3]	319	1			T11	36		T139	30		T66	21
auto[0]	values[3]	values[4]	796	1			T11	20		T33	52		T159	21
auto[0]	values[3]	values[5]	394	1			T29	20		T107	20		T146	21
auto[0]	values[3]	values[6]	421	1			T29	19		T160	24		T161	10
auto[0]	values[3]	values[7]	404	1			T29	31		T107	19		T58	42
auto[0]	values[4]	values[0]	743	1			T29	105		T31	68		T32	41
auto[0]	values[4]	values[1]	367	1			T29	20		T162	4		T58	50
auto[0]	values[4]	values[2]	976	1			T11	19		T29	24		T32	24
auto[0]	values[4]	values[3]	720	1			T11	44		T26	51		T29	22
auto[0]	values[4]	values[4]	563	1			T11	20		T36	16		T32	39
auto[0]	values[4]	values[5]	524	1			T25	38		T29	23		T31	20
auto[0]	values[4]	values[6]	560	1			T11	20		T26	20		T29	21
auto[0]	values[4]	values[7]	320	1			T159	29		T58	66		T163	20
auto[0]	values[5]	values[0]	668	1			T32	44		T159	20		T164	20
auto[0]	values[5]	values[1]	787	1			T31	45		T165	20		T58	20
auto[0]	values[5]	values[2]	596	1			T29	28		T32	20		T33	39
auto[0]	values[5]	values[3]	489	1			T11	39		T29	20		T31	75
auto[0]	values[5]	values[4]	292	1			T166	2		T167	12		T168	10
auto[0]	values[5]	values[5]	547	1			T29	20		T31	52		T32	18
auto[0]	values[5]	values[6]	465	1			T34	87		T58	20		T169	20
auto[0]	values[5]	values[7]	513	1			T11	20		T29	21		T170	20
auto[0]	values[6]	values[0]	704	1			T38	4		T25	113		T29	69
auto[0]	values[6]	values[1]	658	1			T26	92		T29	21		T31	23
auto[0]	values[6]	values[2]	390	1			T8	14		T29	20		T30	20
auto[0]	values[6]	values[3]	652	1			T11	51		T58	22		T146	20
auto[0]	values[6]	values[4]	497	1			T29	58		T34	20		T171	18
auto[0]	values[6]	values[5]	403	1			T29	20		T172	4		T32	20
auto[0]	values[6]	values[6]	572	1			T7	16		T25	18		T29	19
auto[0]	values[6]	values[7]	433	1			T25	23		T29	20		T151	35
auto[0]	values[7]	values[0]	443	1			T31	20		T170	20		T173	28
auto[0]	values[7]	values[1]	512	1			T31	51		T151	18		T32	20
auto[0]	values[7]	values[2]	401	1			T9	6		T29	104		T31	20
auto[0]	values[7]	values[3]	691	1			T25	16		T26	42		T30	19
auto[0]	values[7]	values[4]	388	1			T11	20		T31	61		T151	30
auto[0]	values[7]	values[5]	456	1			T33	20		T154	19		T174	109
auto[0]	values[7]	values[6]	450	1			T25	20		T29	23		T30	20
auto[0]	values[7]	values[7]	452	1			T31	20		T33	40		T175	2
auto[1]	values[0]	values[0]	23	1			T31	3		T159	2		T176	4
auto[1]	values[0]	values[1]	8	1			T66	2		T177	2		T178	1
auto[1]	values[0]	values[2]	6	1			T179	2		T180	3		T181	1
auto[1]	values[0]	values[3]	12	1			T32	5		T182	2		T180	1
auto[1]	values[0]	values[4]	8	1			T146	4		T183	1		T184	3
auto[1]	values[0]	values[5]	7	1			T58	1		T185	3		T186	1
auto[1]	values[0]	values[6]	13	1			T146	2		T173	1		T177	1
auto[1]	values[0]	values[7]	7	1			T173	2		T179	1		T187	2
auto[1]	values[1]	values[0]	7	1			T177	2		T180	1		T188	1
auto[1]	values[1]	values[1]	3	1			T29	2		T180	1		-	-
auto[1]	values[1]	values[2]	11	1			T26	1		T185	2		T189	1
auto[1]	values[1]	values[3]	7	1			T33	1		T150	1		T179	1
auto[1]	values[1]	values[4]	10	1			T11	3		T29	1		T58	2
auto[1]	values[1]	values[5]	11	1			T29	2		T66	1		T159	1
auto[1]	values[1]	values[6]	10	1			T26	1		T144	1		T173	1
auto[1]	values[1]	values[7]	6	1			T185	2		T134	2		T135	2
auto[1]	values[2]	values[0]	13	1			T29	1		T30	1		T154	1
auto[1]	values[2]	values[1]	9	1			T11	1		T31	3		T58	3
auto[1]	values[2]	values[2]	5	1			T11	1		T29	1		T190	1
auto[1]	values[2]	values[3]	18	1			T11	5		T152	2		T190	1
auto[1]	values[2]	values[4]	12	1			T191	4		T192	1		T193	1
auto[1]	values[2]	values[5]	6	1			T146	1		T173	1		T185	3
auto[1]	values[2]	values[6]	13	1			T146	3		T150	2		T173	1
auto[1]	values[2]	values[7]	13	1			T11	1		T58	1		T184	2
auto[1]	values[3]	values[0]	12	1			T29	2		T146	4		T194	1
auto[1]	values[3]	values[1]	10	1			T190	2		T180	1		T187	1
auto[1]	values[3]	values[2]	10	1			T29	3		T154	1		T178	3
auto[1]	values[3]	values[3]	4	1			T66	1		T179	1		T185	2
auto[1]	values[3]	values[4]	6	1			T58	1		T195	1		T131	1
auto[1]	values[3]	values[6]	16	1			T29	1		T160	10		T163	1
auto[1]	values[3]	values[7]	7	1			T29	1		T107	1		T131	2
auto[1]	values[4]	values[0]	17	1			T29	1		T31	2		T164	6
auto[1]	values[4]	values[1]	8	1			T58	2		T152	1		T191	1
auto[1]	values[4]	values[2]	18	1			T11	1		T33	1		T192	3
auto[1]	values[4]	values[3]	12	1			T11	1		T159	1		T186	4
auto[1]	values[4]	values[4]	8	1			T11	1		T32	1		T150	1
auto[1]	values[4]	values[5]	16	1			T25	2		T29	1		T33	1
auto[1]	values[4]	values[6]	6	1			T31	2		T187	2		T196	2
auto[1]	values[4]	values[7]	4	1			T179	1		T180	1		T135	1
auto[1]	values[5]	values[0]	18	1			T32	1		T159	1		T183	1
auto[1]	values[5]	values[1]	18	1			T31	3		T165	6		T177	1
auto[1]	values[5]	values[2]	9	1			T197	4		T180	2		T68	1
auto[1]	values[5]	values[3]	1	1			T163	1		-	-		-	-
auto[1]	values[5]	values[4]	6	1			T150	2		T195	2		T182	2
auto[1]	values[5]	values[5]	14	1			T32	4		T35	4		T198	2
auto[1]	values[5]	values[6]	7	1			T34	3		T58	1		T185	1
auto[1]	values[5]	values[7]	15	1			T29	2		T144	3		T146	3
auto[1]	values[6]	values[0]	7	1			T29	2		T32	1		T150	1
auto[1]	values[6]	values[1]	16	1			T26	1		T32	1		T199	4
auto[1]	values[6]	values[2]	6	1			T200	1		T67	2		T68	2
auto[1]	values[6]	values[3]	7	1			T11	1		T192	3		T201	3
auto[1]	values[6]	values[4]	8	1			T171	2		T144	1		T192	1
auto[1]	values[6]	values[5]	8	1			T131	1		T202	2		T134	3
auto[1]	values[6]	values[6]	11	1			T25	2		T29	1		T203	4
auto[1]	values[6]	values[7]	8	1			T25	1		T66	1		T150	1
auto[1]	values[7]	values[0]	4	1			T179	1		T204	1		T205	2
auto[1]	values[7]	values[1]	9	1			T151	3		T177	1		T179	1
auto[1]	values[7]	values[2]	10	1			T29	1		T33	2		T58	2
auto[1]	values[7]	values[3]	18	1			T25	4		T26	2		T30	1
auto[1]	values[7]	values[4]	13	1			T31	2		T151	1		T182	2
auto[1]	values[7]	values[5]	8	1			T154	1		T192	2		T187	3
auto[1]	values[7]	values[6]	8	1			T192	1		T131	2		T206	2
auto[1]	values[7]	values[7]	7	1			T34	1		T178	5		T184	1