Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2635

1

T1

3

T3

12

T14

9

auto[1]

2709

1

T1

5

T3

5

T14

21

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2927

1

T1

7

T3

17

T11

13

auto[1]

2417

1

T1

1

T14

30

T11

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4200

1

T1

4

T3

13

T14

30

auto[1]

1144

1

T1

4

T3

4

T11

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1043	1			T1	1		T3	6		T14	2
valid[1]	1136	1			T1	2		T3	2		T14	7
valid[2]	1033	1			T1	1		T3	4		T14	9
valid[3]	1096	1			T1	2		T3	2		T14	4
valid[4]	1036	1			T1	2		T3	3		T14	8

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	145	1			T3	2		T18	1		T25	1
auto[0]	auto[0]	valid[0]	auto[1]	238	1			T14	1		T17	1		T70	8
auto[0]	auto[0]	valid[1]	auto[0]	166	1			T1	1		T3	1		T11	1
auto[0]	auto[0]	valid[1]	auto[1]	262	1			T17	5		T70	4		T72	1
auto[0]	auto[0]	valid[2]	auto[0]	184	1			T3	3		T11	1		T25	1
auto[0]	auto[0]	valid[2]	auto[1]	236	1			T14	3		T17	1		T27	2
auto[0]	auto[0]	valid[3]	auto[0]	164	1			T3	2		T11	1		T27	2
auto[0]	auto[0]	valid[3]	auto[1]	253	1			T14	1		T17	1		T27	1
auto[0]	auto[0]	valid[4]	auto[0]	159	1			T3	1		T16	1		T25	1
auto[0]	auto[0]	valid[4]	auto[1]	250	1			T1	1		T14	4		T11	2
auto[0]	auto[1]	valid[0]	auto[0]	192	1			T1	1		T3	3		T11	1
auto[0]	auto[1]	valid[0]	auto[1]	221	1			T14	1		T17	1		T27	1
auto[0]	auto[1]	valid[1]	auto[0]	196	1			T16	2		T29	1		T120	3
auto[0]	auto[1]	valid[1]	auto[1]	259	1			T14	7		T11	1		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	185	1			T11	1		T62	3		T29	1
auto[0]	auto[1]	valid[2]	auto[1]	242	1			T14	6		T11	1		T16	1
auto[0]	auto[1]	valid[3]	auto[0]	211	1			T11	1		T18	1		T62	1
auto[0]	auto[1]	valid[3]	auto[1]	231	1			T14	3		T16	2		T17	1
auto[0]	auto[1]	valid[4]	auto[0]	181	1			T1	1		T3	1		T11	2
auto[0]	auto[1]	valid[4]	auto[1]	225	1			T14	4		T11	1		T16	1
auto[1]	auto[0]	valid[0]	auto[0]	122	1			T11	2		T16	1		T18	1
auto[1]	auto[0]	valid[1]	auto[0]	125	1			T3	1		T11	1		T27	1
auto[1]	auto[0]	valid[2]	auto[0]	99	1			T3	1		T29	1		T120	1
auto[1]	auto[0]	valid[3]	auto[0]	120	1			T1	1		T16	2		T27	1
auto[1]	auto[0]	valid[4]	auto[0]	112	1			T3	1		T16	1		T27	1
auto[1]	auto[1]	valid[0]	auto[0]	125	1			T3	1		T25	1		T29	2
auto[1]	auto[1]	valid[1]	auto[0]	128	1			T1	1		T16	1		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	87	1			T1	1		T18	1		T29	1
auto[1]	auto[1]	valid[3]	auto[0]	117	1			T1	1		T11	2		T16	1
auto[1]	auto[1]	valid[4]	auto[0]	109	1			T29	1		T69	1		T106	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal