Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74182

1

T1

246

T3

305

T11

379

auto[1]

25703

1

T1

31

T14

340

T11

19

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72397

1

T1

173

T3

206

T14

340

auto[1]

27488

1

T1

104

T3

99

T11

127

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	51381	1			T1	149		T3	173		T14	175
others[1]	8359	1			T1	20		T3	19		T14	25
others[2]	8435	1			T1	20		T3	25		T14	23
others[3]	9701	1			T1	21		T3	24		T14	40
interest[1]	5442	1			T1	23		T3	15		T14	18
interest[4]	33491	1			T1	101		T3	104		T14	106
interest[64]	16567	1			T1	44		T3	49		T14	59

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23753	1			T1	74		T3	112		T11	120
auto[0]	auto[0]	others[1]	3869	1			T1	9		T3	13		T11	25
auto[0]	auto[0]	others[2]	4020	1			T1	11		T3	17		T11	16
auto[0]	auto[0]	others[3]	4611	1			T1	11		T3	16		T11	30
auto[0]	auto[0]	interest[1]	2615	1			T1	10		T3	10		T11	11
auto[0]	auto[0]	interest[4]	15324	1			T1	52		T3	69		T11	82
auto[0]	auto[0]	interest[64]	7826	1			T1	27		T3	38		T11	50
auto[0]	auto[1]	others[0]	13465	1			T1	18		T14	175		T11	12
auto[0]	auto[1]	others[1]	2157	1			T1	3		T14	25		T11	3
auto[0]	auto[1]	others[2]	2109	1			T1	2		T14	23		T11	1
auto[0]	auto[1]	others[3]	2378	1			T1	3		T14	40		T11	1
auto[0]	auto[1]	interest[1]	1370	1			T1	2		T14	18		T16	6
auto[0]	auto[1]	interest[4]	8934	1			T1	8		T14	106		T11	6
auto[0]	auto[1]	interest[64]	4224	1			T1	3		T14	59		T11	2
auto[1]	auto[0]	others[0]	14163	1			T1	57		T3	61		T11	66
auto[1]	auto[0]	others[1]	2333	1			T1	8		T3	6		T11	12
auto[1]	auto[0]	others[2]	2306	1			T1	7		T3	8		T11	7
auto[1]	auto[0]	others[3]	2712	1			T1	7		T3	8		T11	11
auto[1]	auto[0]	interest[1]	1457	1			T1	11		T3	5		T11	12
auto[1]	auto[0]	interest[4]	9233	1			T1	41		T3	35		T11	38
auto[1]	auto[0]	interest[64]	4517	1			T1	14		T3	11		T11	19

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal