Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	2	34	94.44

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	2	34	94.44	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	779	1			T11	30		T27	8		T29	10
all_values[1]	779	1			T11	30		T27	8		T29	10
all_values[2]	779	1			T11	30		T27	8		T29	10
all_values[3]	779	1			T11	30		T27	8		T29	10
all_values[4]	779	1			T11	30		T27	8		T29	10
all_values[5]	779	1			T11	30		T27	8		T29	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2526

1

T11

103

T27

30

T29

33

auto[1]

2148

1

T11

77

T27

18

T29

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1881

1

T11

69

T27

26

T29

19

auto[1]

2793

1

T11

111

T27

22

T29

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2633

1

T11

97

T27

31

T29

27

auto[1]

2041

1

T11

83

T27

17

T29

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	2	34	94.44	2
Automatically Generated Cross Bins	36	2	34	94.44	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T11	6		T27	2		T29	1
all_values[0]	auto[0]	auto[0]	auto[1]	68	1			T11	1		T129	1		T137	1
all_values[0]	auto[0]	auto[1]	auto[0]	138	1			T11	7		T27	2		T29	4
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T11	4		T27	1		T29	1
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T11	5		T27	2		T29	4
all_values[0]	auto[1]	auto[1]	auto[1]	151	1			T11	7		T27	1		T138	1
all_values[1]	auto[0]	auto[0]	auto[0]	144	1			T11	5		T27	2		T32	3
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T11	3		T29	3		T129	1
all_values[1]	auto[0]	auto[1]	auto[0]	129	1			T11	2		T27	3		T29	2
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T11	2		T27	1		T129	3
all_values[1]	auto[1]	auto[0]	auto[1]	178	1			T11	12		T27	1		T29	3
all_values[1]	auto[1]	auto[1]	auto[1]	167	1			T11	6		T27	1		T29	2
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T11	5		T27	3		T29	1
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T11	6		T29	1		T32	2
all_values[2]	auto[0]	auto[1]	auto[0]	136	1			T11	4		T27	1		T32	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T11	2		T27	1		T29	1
all_values[2]	auto[1]	auto[0]	auto[1]	172	1			T11	9		T27	2		T29	4
all_values[2]	auto[1]	auto[1]	auto[1]	172	1			T11	4		T27	1		T29	3
all_values[3]	auto[0]	auto[0]	auto[0]	151	1			T11	8		T27	3		T29	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T11	2		T29	1		T137	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T11	7		T27	1		T29	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T27	1		T129	3		T137	1
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T11	10		T27	2		T29	4
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T11	3		T27	1		T29	3
all_values[4]	auto[0]	auto[0]	auto[0]	174	1			T11	3		T27	5		T29	2
all_values[4]	auto[0]	auto[0]	auto[1]	64	1			T11	4		T27	1		T29	1
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T11	3		T29	2		T32	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T11	4		T32	1		T129	2
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T11	7		T27	1		T29	3
all_values[4]	auto[1]	auto[1]	auto[1]	141	1			T11	9		T27	1		T29	2
all_values[5]	auto[0]	auto[0]	auto[0]	270	1			T11	10		T27	3		T29	3
all_values[5]	auto[0]	auto[1]	auto[0]	167	1			T11	9		T27	1		T29	2
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T11	7		T27	3		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T11	4		T27	1		T29	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal