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 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT73,T74,T75
11CoveredT1,T3,T4

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T49,T50
10CoveredT73,T77,T78

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT48,T49,T50
010CoveredT73,T77,T78
100CoveredT48,T49,T50

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:7423]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[7680:8063]}) ? 2'b1 : 2'd2))
             ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       132
 SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[7680:8063]}) ? 2'b1 : 2'd2)
                 ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       171
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT73,T77,T78
010CoveredT74,T75,T76
100CoveredT74,T75,T76

 LINE       19307
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_STATE_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       19308
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_ENABLE_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T11

 LINE       19309
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_TEST_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T11

 LINE       19310
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ALERT_TEST_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       19311
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CONTROL_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19312
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CFG_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19313
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_STATUS_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T13

 LINE       19314
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTERCEPT_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19315
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_MODE_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19316
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_LAST_READ_ADDR_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19317
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_FLASH_STATUS_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19318
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_CC_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19319
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_ID_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19320
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_READ_THRESHOLD_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19321
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_MAILBOX_ADDR_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19322
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19323
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS2_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       19324
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19325
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       19326
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19327
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_1_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19328
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_2_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19329
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_3_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19330
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_4_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19331
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_5_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19332
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_6_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19333
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_7_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19334
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_MASK_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19335
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_DATA_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19336
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19337
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19338
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_0_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19339
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_1_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19340
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_2_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19341
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_3_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19342
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_4_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19343
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_5_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19344
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_6_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19345
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_7_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19346
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_8_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19347
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_9_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19348
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_10_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19349
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_11_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19350
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_12_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19351
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_13_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19352
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_14_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19353
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_15_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19354
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_16_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19355
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_17_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19356
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_18_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19357
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_19_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19358
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_20_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19359
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_21_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19360
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_22_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19361
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_23_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19362
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EN4B_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19363
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EX4B_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19364
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WREN_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19365
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WRDI_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19366
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CAP_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T39

 LINE       19367
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CFG_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19368
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STATUS_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19369
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19370
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_1_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19371
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STS_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19372
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       19373
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_ENABLE_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19374
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_VECTOR_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19375
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_STATUS_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19376
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_DID_VID_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19377
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_RID_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19378
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CMD_ADDR_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       19379
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_READ_FIFO_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11

 LINE       19380
 EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_WRITE_FIFO_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       19383
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       19383
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       19387
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[59] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT74,T75,T76

 LINE       19387
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b0111 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | 
     62  (addr_hit[61] & ((|(4'b0111 & (~reg_be))))) | 
     63  (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | 
     64  (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | 
     65  (addr_hit[64] & ((|(4'b1111 & (~reg_be))))) | 
     66  (addr_hit[65] & ((|(4'b1111 & (~reg_be))))) | 
     67  (addr_hit[66] & ((|(4'b1111 & (~reg_be))))) | 
     68  (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | 
     69  (addr_hit[68] & ((|(4'b1111 & (~reg_be))))) | 
     70  (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) | 
     71  (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | 
     72  (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) | 
     73  (addr_hit[72] & ((|(4'b1111 & (~reg_be))))) | 
     74  (addr_hit[73] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
74 (addr_hit[73] & ((|(4'...CoveredT1,T3,T11
73 (addr_hit[72] & ((|(4'...CoveredT1,T62,T39
72 (addr_hit[71] & ((|(4'...CoveredT1,T3,T11
71 (addr_hit[70] & ((|(4'...CoveredT1,T69,T32
70 (addr_hit[69] & ((|(4'...CoveredT1,T14,T62
69 (addr_hit[68] & ((|(4'...CoveredT1,T62,T39
68 (addr_hit[67] & ((|(4'...CoveredT1,T62,T79
67 (addr_hit[66] & ((|(4'...CoveredT1,T69,T41
66 (addr_hit[65] & ((|(4'...CoveredT1,T4,T62
65 (addr_hit[64] & ((|(4'...CoveredT1,T62,T39
64 (addr_hit[63] & ((|(4'...CoveredT1,T62,T79
63 (addr_hit[62] & ((|(4'...CoveredT1,T62,T39
62 (addr_hit[61] & ((|(4'...CoveredT1,T3,T14
61 (addr_hit[60] & ((|(4'...CoveredT1,T14,T39
60 (addr_hit[59] & ((|(4'...CoveredT1,T4,T39
59 (addr_hit[58] & ((|(4'...CoveredT1,T62,T39
58 (addr_hit[57] & ((|(4'...CoveredT1,T79,T39
57 (addr_hit[56] & ((|(4'...CoveredT1,T4,T62
56 (addr_hit[55] & ((|(4'...CoveredT1,T79,T39
55 (addr_hit[54] & ((|(4'...CoveredT1,T4,T62
54 (addr_hit[53] & ((|(4'...CoveredT1,T62,T79
53 (addr_hit[52] & ((|(4'...CoveredT1,T62,T69
52 (addr_hit[51] & ((|(4'...CoveredT1,T4,T14
51 (addr_hit[50] & ((|(4'...CoveredT1,T4,T62
50 (addr_hit[49] & ((|(4'...CoveredT1,T62,T39
49 (addr_hit[48] & ((|(4'...CoveredT1,T14,T69
48 (addr_hit[47] & ((|(4'...CoveredT1,T39,T69
47 (addr_hit[46] & ((|(4'...CoveredT1,T62,T39
46 (addr_hit[45] & ((|(4'...CoveredT1,T62,T39
45 (addr_hit[44] & ((|(4'...CoveredT1,T62,T79
44 (addr_hit[43] & ((|(4'...CoveredT1,T4,T62
43 (addr_hit[42] & ((|(4'...CoveredT1,T62,T79
42 (addr_hit[41] & ((|(4'...CoveredT1,T62,T69
41 (addr_hit[40] & ((|(4'...CoveredT1,T62,T79
40 (addr_hit[39] & ((|(4'...CoveredT1,T4,T62
39 (addr_hit[38] & ((|(4'...CoveredT1,T4,T14
38 (addr_hit[37] & ((|(4'...CoveredT1,T62,T39
37 (addr_hit[36] & ((|(4'...CoveredT1,T79,T39
36 (addr_hit[35] & ((|(4'...CoveredT1,T14,T62
35 (addr_hit[34] & ((|(4'...CoveredT1,T39,T69
34 (addr_hit[33] & ((|(4'...CoveredT1,T62,T39
33 (addr_hit[32] & ((|(4'...CoveredT1,T69,T40
32 (addr_hit[31] & ((|(4'...CoveredT1,T14,T39
31 (addr_hit[30] & ((|(4'...CoveredT1,T14,T62
30 (addr_hit[29] & ((|(4'...CoveredT1,T4,T62
29 (addr_hit[28] & ((|(4'...CoveredT1,T62,T39
28 (addr_hit[27] & ((|(4'...CoveredT1,T4,T62
27 (addr_hit[26] & ((|(4'...CoveredT1,T39,T69
26 (addr_hit[25] & ((|(4'...CoveredT1,T62,T79
25 (addr_hit[24] & ((|(4'...CoveredT1,T62,T79
24 (addr_hit[23] & ((|(4'...CoveredT1,T14,T62
23 (addr_hit[22] & ((|(4'...CoveredT1,T14,T79
22 (addr_hit[21] & ((|(4'...CoveredT1,T4,T14
21 (addr_hit[20] & ((|(4'...CoveredT1,T4,T62
20 (addr_hit[19] & ((|(4'...CoveredT1,T14,T62
19 (addr_hit[18] & ((|(4'...CoveredT1,T3,T11
18 (addr_hit[17] & ((|(4'...CoveredT1,T3,T14
17 (addr_hit[16] & ((|(4'...CoveredT1,T3,T11
16 (addr_hit[15] & ((|(4'...CoveredT1,T3,T4
15 (addr_hit[14] & ((|(4'...CoveredT1,T62,T39
14 (addr_hit[13] & ((|(4'...CoveredT1,T62,T39
13 (addr_hit[12] & ((|(4'...CoveredT1,T14,T62
12 (addr_hit[11] & ((|(4'...CoveredT1,T4,T62
11 (addr_hit[10] & ((|(4'...CoveredT1,T3,T4
10 (addr_hit[9] & ((|(4'b...CoveredT1,T3,T5
9 (addr_hit[8] & ((|(4'b...CoveredT1,T3,T4
8 (addr_hit[7] & ((|(4'b...CoveredT1,T39,T69
7 (addr_hit[6] & ((|(4'b...CoveredT1,T69,T32
6 (addr_hit[5] & ((|(4'b...CoveredT1,T4,T79
5 (addr_hit[4] & ((|(4'b...CoveredT1,T4,T39
4 (addr_hit[3] & ((|(4'b...CoveredT1,T39,T69
3 (addr_hit[2] & ((|(4'b...CoveredT1,T11,T39
2 (addr_hit[1] & ((|(4'b...CoveredT1,T11,T27
1 (addr_hit[0] & ((|(4'b...CoveredT1,T3,T4

 LINE       19387
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       19387
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T11
11CoveredT1,T11,T27

 LINE       19387
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T11
11CoveredT1,T11,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T6
11CoveredT1,T39,T69

 LINE       19387
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T4,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T4,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T13
11CoveredT1,T69,T32

 LINE       19387
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T39,T69

 LINE       19387
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       19387
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T5

 LINE       19387
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       19387
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T11
11CoveredT1,T3,T4

 LINE       19387
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T11
11CoveredT1,T3,T11

 LINE       19387
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T14
11CoveredT1,T3,T14

 LINE       19387
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T11
11CoveredT1,T3,T11

 LINE       19387
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T14

 LINE       19387
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T39,T69

 LINE       19387
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T69,T40

 LINE       19387
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T39,T69

 LINE       19387
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T14,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T79,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39

 LINE       19387
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T14

 LINE       19387
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T69

 LINE       19387
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T4,T62

 LINE       19387
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T79

 LINE       19387
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T62,T39
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%