Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7419162	1			T1	1		T2	128373		T3	1
all_values[1]	7419162	1			T1	1		T2	128373		T3	1
all_values[2]	7419162	1			T1	1		T2	128373		T3	1
all_values[3]	7419162	1			T1	1		T2	128373		T3	1
all_values[4]	7419162	1			T1	1		T2	128373		T3	1
all_values[5]	7419162	1			T1	1		T2	128373		T3	1
all_values[6]	7419162	1			T1	1		T2	128373		T3	1
all_values[7]	7419162	1			T1	1		T2	128373		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57651198

1

T1

8

T2

102690

T3

8

auto[1]

1702098

1

T2

79

T36

64

T27

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59276254

1

T1

8

T2

102620

T3

8

auto[1]

77042

1

T2

778

T8

403

T9

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6954255	1			T1	1		T2	127970		T3	1
all_values[0]	auto[0]	auto[1]	41643	1			T2	395		T8	239		T16	282
all_values[0]	auto[1]	auto[0]	421288	1			T2	4		T36	6		T27	3
all_values[0]	auto[1]	auto[1]	1976	1			T2	4		T36	3		T37	2
all_values[1]	auto[0]	auto[0]	7031912	1			T1	1		T2	128152		T3	1
all_values[1]	auto[0]	auto[1]	21609	1			T2	212		T8	148		T16	63
all_values[1]	auto[1]	auto[0]	364740	1			T2	4		T36	7		T27	3
all_values[1]	auto[1]	auto[1]	901	1			T2	5		T36	4		T37	2
all_values[2]	auto[0]	auto[0]	7105220	1			T1	1		T2	128261		T3	1
all_values[2]	auto[0]	auto[1]	8171	1			T2	107		T8	16		T16	21
all_values[2]	auto[1]	auto[0]	305313	1			T2	2		T36	5		T27	1
all_values[2]	auto[1]	auto[1]	458	1			T2	3		T36	1		T37	2
all_values[3]	auto[0]	auto[0]	7234210	1			T1	1		T2	128354		T3	1
all_values[3]	auto[0]	auto[1]	211	1			T2	8		T36	5		T37	2
all_values[3]	auto[1]	auto[0]	184502	1			T2	8		T36	6		T27	1
all_values[3]	auto[1]	auto[1]	239	1			T2	3		T36	6		T27	2
all_values[4]	auto[0]	auto[0]	7275841	1			T1	1		T2	128354		T3	1
all_values[4]	auto[0]	auto[1]	231	1			T2	5		T36	9		T37	1
all_values[4]	auto[1]	auto[0]	142874	1			T2	4		T27	1		T37	9
all_values[4]	auto[1]	auto[1]	216	1			T2	10		T36	3		T37	2
all_values[5]	auto[0]	auto[0]	7356978	1			T1	1		T2	128360		T3	1
all_values[5]	auto[0]	auto[1]	385	1			T2	2		T9	3		T36	2
all_values[5]	auto[1]	auto[0]	61611	1			T2	8		T36	11		T27	1
all_values[5]	auto[1]	auto[1]	188	1			T2	3		T36	3		T27	1
all_values[6]	auto[0]	auto[0]	7349884	1			T1	1		T2	128358		T3	1
all_values[6]	auto[0]	auto[1]	187	1			T2	5		T36	1		T37	2
all_values[6]	auto[1]	auto[0]	68900	1			T2	3		T36	5		T27	5
all_values[6]	auto[1]	auto[1]	191	1			T2	7		T36	2		T37	1
all_values[7]	auto[0]	auto[0]	7270237	1			T1	1		T2	128358		T3	1
all_values[7]	auto[0]	auto[1]	224	1			T2	4		T36	8		T27	1
all_values[7]	auto[1]	auto[0]	148489	1			T2	6		T36	1		T27	4
all_values[7]	auto[1]	auto[1]	212	1			T2	5		T36	1		T37	2