Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38881	1			T2	136		T8	539		T10	25
auto[SpiFlashAddrCfg]	8897	1			T2	63		T4	10		T8	58
auto[SpiFlashAddr3b]	10762	1			T2	55		T4	10		T8	61
auto[SpiFlashAddr4b]	9046	1			T2	64		T8	62		T10	7

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39775

1

T2

165

T4

20

T8

275

auto[1]

27811

1

T2

153

T8

445

T10

19

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35743

1

T2

186

T4

12

T8

385

auto[1]

31843

1

T2

132

T4

8

T8

335

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44207	1			T2	198		T8	583		T10	32
values[1]	1321	1			T2	8		T8	5		T10	4
values[2]	1690	1			T2	3		T4	4		T8	7
values[3]	1806	1			T2	5		T8	9		T14	4
values[4]	1686	1			T2	11		T8	8		T10	4
values[5]	1705	1			T2	11		T8	13		T16	10
values[6]	1668	1			T2	13		T4	6		T8	8
values[7]	1893	1			T2	12		T4	2		T8	13
values[8]	11610	1			T2	57		T4	8		T8	74

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33163

1

T2

318

T4

20

T11

61

auto[1]

34423

1

T8

720

T10

60

T57

243

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

65104

1

T2

297

T4

20

T8

704

write

2482

1

T2

21

T8

16

T10

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23330

1

T2

119

T4

12

T8

153

valids[0x1]

44256

1

T2

199

T4

8

T8

567

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1826	1			T2	7		T8	12		T10	4
internal_process_ops[0x5a]	1807	1			T2	12		T8	9		T10	4
internal_process_ops[0x05]	22720	1			T2	63		T8	430		T10	2
internal_process_ops[0x35]	1879	1			T2	13		T8	10		T10	3
internal_process_ops[0x15]	1845	1			T2	9		T8	9		T10	2
internal_process_ops[0x03]	1209	1			T2	13		T4	6		T8	3
internal_process_ops[0x0b]	1196	1			T2	9		T4	2		T8	3
internal_process_ops[0x3b]	1219	1			T2	8		T4	4		T8	3
internal_process_ops[0x6b]	1260	1			T2	8		T4	4		T8	6
internal_process_ops[0xbb]	1301	1			T2	8		T4	4		T8	2
internal_process_ops[0xeb]	1351	1			T2	7		T8	4		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66415

1

T2

305

T4

20

T8

712

auto[1]

1171

1

T2

13

T8

8

T10

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65189

1

T2

304

T4

20

T8

705

auto[1]

2397

1

T2

14

T8

15

T11

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11755

1

T2

65

T11

55

T13

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6190

1

T2

69

T15

2

T16

77

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2336

1

T2

28

T4

10

T14

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1954

1

T2

23

T15

10

T16

28

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2817

1

T2

27

T4

10

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2420

1

T2

25

T15

12

T16

42

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2292

1

T2

37

T11

2

T16

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2219

1

T2

23

T15

10

T16

37

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T16

1

T73

2

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

56

1

T18

1

T29

2

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T16

3

T154

4

T159

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

77

1

T2

2

T16

6

T18

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

82

1

T2

7

T16

2

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T2

1

T16

1

T27

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

69

1

T56

1

T27

1

T31

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T2

4

T28

2

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

98

1

T11

2

T27

1

T155

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T16

2

T18

2

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T2

1

T18

1

T56

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

62

1

T2

2

T18

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

101

1

T30

1

T155

1

T159

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

60

1

T18

4

T29

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

52

1

T16

2

T27

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T2

4

T27

1

T51

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12676

1

T8

176

T10

23

T57

69

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7661

1

T8

357

T10

1

T57

48

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2073

1

T8

28

T10

2

T57

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1917

1

T8

27

T10

8

T57

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2510

1

T8

27

T10

11

T57

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2369

1

T8

31

T10

7

T57

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2026

1

T8

32

T10

4

T57

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1889

1

T8

26

T10

3

T57

27

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

76

1

T8

2

T58

1

T67

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T8

3

T10

1

T57

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T8

1

T58

2

T51

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

69

1

T57

1

T58

1

T153

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T8

1

T58

1

T51

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T57

3

T154

2

T51

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T153

1

T51

1

T67

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

70

1

T8

2

T58

1

T153

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T8

1

T58

6

T51

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T8

1

T58

2

T51

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T57

1

T48

2

T51

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T8

1

T153

1

T51

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T8

3

T51

9

T67

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T8

1

T57

2

T51

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T153

1

T51

3

T67

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

73

1

T153

3

T51

6

T67

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4485	1			T2	48		T11	6		T15	4
auto[0]	values[0]	valids[0x1]	16396	1			T2	150		T11	55		T13	2
auto[0]	values[1]	valids[0x1]	633	1			T2	8		T16	5		T73	2
auto[0]	values[2]	valids[0x0]	572	1			T2	2		T4	4		T16	9
auto[0]	values[2]	valids[0x1]	311	1			T2	1		T16	6		T18	6
auto[0]	values[3]	valids[0x0]	633	1			T2	3		T14	4		T16	3
auto[0]	values[3]	valids[0x1]	333	1			T2	2		T15	6		T16	5
auto[0]	values[4]	valids[0x0]	520	1			T2	11		T16	7		T18	3
auto[0]	values[4]	valids[0x1]	312	1			T16	4		T18	4		T26	1
auto[0]	values[5]	valids[0x0]	573	1			T2	6		T16	2		T18	7
auto[0]	values[5]	valids[0x1]	314	1			T2	5		T16	8		T18	5
auto[0]	values[6]	valids[0x0]	545	1			T2	11		T16	8		T18	7
auto[0]	values[6]	valids[0x1]	335	1			T2	2		T4	6		T16	3
auto[0]	values[7]	valids[0x0]	694	1			T2	6		T16	13		T18	15
auto[0]	values[7]	valids[0x1]	349	1			T2	6		T4	2		T14	4
auto[0]	values[8]	valids[0x0]	3931	1			T2	32		T4	8		T14	4
auto[0]	values[8]	valids[0x1]	2227	1			T2	25		T15	8		T16	27
auto[1]	values[0]	valids[0x0]	5032	1			T8	78		T10	12		T57	40
auto[1]	values[0]	valids[0x1]	18294	1			T8	505		T10	20		T57	99
auto[1]	values[1]	valids[0x1]	688	1			T8	5		T10	4		T57	5
auto[1]	values[2]	valids[0x0]	506	1			T8	5		T10	3		T57	7
auto[1]	values[2]	valids[0x1]	301	1			T8	2		T10	3		T57	1
auto[1]	values[3]	valids[0x0]	487	1			T8	6		T57	3		T58	5
auto[1]	values[3]	valids[0x1]	353	1			T8	3		T57	10		T58	2
auto[1]	values[4]	valids[0x0]	528	1			T8	3		T10	2		T57	1
auto[1]	values[4]	valids[0x1]	326	1			T8	5		T10	2		T57	4
auto[1]	values[5]	valids[0x0]	508	1			T8	3		T57	3		T58	12
auto[1]	values[5]	valids[0x1]	310	1			T8	10		T57	2		T153	2
auto[1]	values[6]	valids[0x0]	499	1			T8	5		T57	9		T58	5
auto[1]	values[6]	valids[0x1]	289	1			T8	3		T57	4		T58	1
auto[1]	values[7]	valids[0x0]	524	1			T8	12		T57	4		T58	5
auto[1]	values[7]	valids[0x1]	326	1			T8	1		T57	1		T58	4
auto[1]	values[8]	valids[0x0]	3293	1			T8	41		T10	6		T57	28
auto[1]	values[8]	valids[0x1]	2159	1			T8	33		T10	8		T57	22