Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19001

1

T2

95

T4

12

T8

105

auto[1]

23013

1

T2

70

T8

435

T11

46

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15866

1

T2

80

T4

12

T8

91

auto[1]

26148

1

T2

85

T8

449

T10

7

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7105	1			T2	32		T4	3		T8	51
auto[524288:1048575]	4534	1			T2	20		T4	2		T8	4
auto[1048576:1572863]	4943	1			T2	7		T4	1		T8	82
auto[1572864:2097151]	4531	1			T2	35		T4	1		T8	61
auto[2097152:2621439]	5550	1			T2	39		T4	1		T8	221
auto[2621440:3145727]	4937	1			T2	6		T4	1		T8	78
auto[3145728:3670015]	5323	1			T2	8		T8	5		T10	20
auto[3670016:4194303]	5091	1			T2	18		T4	3		T8	38

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41087

1

T2

162

T4

12

T8

531

auto[1]

927

1

T2

3

T8

9

T11

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33845

1

T2

111

T4

12

T8

407

auto[1]

8169

1

T2

54

T8

133

T10

7

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1824	1			T2	4		T4	3		T8	17
auto[0]	auto[0]	auto[0:524287]	auto[1]	744	1			T2	6		T8	1		T11	7
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1280	1			T2	6		T4	2		T8	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	526	1			T2	3		T8	1		T16	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1298	1			T2	5		T4	1		T8	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	484	1			T8	2		T18	5		T27	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1181	1			T2	12		T4	1		T8	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	488	1			T2	6		T8	3		T16	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1325	1			T2	9		T4	1		T8	15
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	518	1			T2	2		T8	6		T16	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1263	1			T2	5		T4	1		T8	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	506	1			T2	1		T8	2		T13	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1389	1			T2	5		T8	5		T10	11
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	530	1			T2	3		T10	3		T18	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1343	1			T2	8		T4	3		T8	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	530	1			T2	1		T8	4		T16	6
auto[0]	auto[1]	auto[0:524287]	auto[0]	324	1			T2	2		T8	5		T16	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	149	1			T2	1		T8	3		T18	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	316	1			T16	1		T18	2		T180	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	156	1			T10	1		T18	1		T27	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	292	1			T117	1		T180	5		T57	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	129	1			T18	1		T57	1		T27	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	282	1			T2	3		T16	1		T117	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	136	1			T2	4		T16	1		T18	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	371	1			T2	7		T8	4		T16	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	157	1			T2	2		T8	4		T16	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	284	1			T8	5		T16	6		T18	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	156	1			T8	2		T16	5		T18	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	387	1			T10	3		T16	5		T117	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	174	1			T10	3		T16	5		T18	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	308	1			T18	3		T56	2		T57	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	151	1			T8	1		T18	1		T57	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	316	1			T2	1		T8	3		T11	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	3170	1			T2	2		T8	22		T11	42
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	225	1			T2	1		T16	1		T18	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1531	1			T2	10		T16	16		T18	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	231	1			T2	1		T8	2		T56	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2093	1			T2	1		T8	76		T56	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	201	1			T2	3		T8	2		T16	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1739	1			T2	7		T8	45		T16	10
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	221	1			T8	4		T16	1		T18	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2152	1			T8	127		T16	1		T18	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	230	1			T8	1		T16	4		T18	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1888	1			T8	14		T16	9		T18	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	248	1			T18	1		T57	1		T27	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2024	1			T18	8		T57	4		T27	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	270	1			T2	4		T8	1		T16	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2077	1			T2	5		T8	29		T16	12
auto[1]	auto[1]	auto[0:524287]	auto[0]	51	1			T2	2		T16	1		T57	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	527	1			T2	14		T16	1		T57	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	63	1			T27	2		T29	1		T153	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	437	1			T27	28		T29	1		T153	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	46	1			T27	1		T154	1		T159	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	370	1			T27	9		T154	3		T159	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	48	1			T16	1		T18	2		T57	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	456	1			T16	2		T18	29		T57	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	81	1			T2	2		T8	1		T18	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	725	1			T2	17		T8	60		T18	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	51	1			T8	1		T16	1		T57	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	559	1			T8	47		T16	18		T57	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T18	1		T31	1		T154	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	502	1			T18	6		T31	1		T154	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	48	1			T29	1		T32	1		T154	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	364	1			T29	7		T32	5		T154	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14866	1			T2	76		T4	12		T8	75
auto[0]	auto[0]	auto[1]	363	1			T8	6		T11	2		T16	3
auto[0]	auto[1]	auto[0]	3691	1			T2	18		T8	23		T10	7
auto[0]	auto[1]	auto[1]	81	1			T2	1		T8	1		T18	2
auto[1]	auto[0]	auto[0]	18239	1			T2	34		T8	324		T11	44
auto[1]	auto[0]	auto[1]	377	1			T2	1		T8	2		T11	2
auto[1]	auto[1]	auto[0]	4291	1			T2	34		T8	109		T16	23
auto[1]	auto[1]	auto[1]	106	1			T2	1		T16	1		T18	1