Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19826

1

T2

165

T4

20

T11

61

auto[1]

13337

1

T2

153

T15

34

T16

195

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4048	1			T2	20		T15	34		T16	20
values[1]	4541	1			T16	40		T18	20		T84	22
values[2]	4582	1			T2	42		T11	61		T16	87
values[3]	3903	1			T2	123		T14	12		T16	42
values[4]	3779	1			T2	44		T16	41		T18	67
values[5]	5040	1			T2	25		T16	113		T18	94
values[6]	3863	1			T2	20		T16	43		T117	8
values[7]	3407	1			T2	44		T4	20		T13	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3786	1			T2	60		T14	12		T16	40
values[1]	3834	1			T4	20		T16	21		T18	60
values[2]	3428	1			T2	59		T16	42		T18	71
values[3]	4689	1			T16	42		T18	47		T191	6
values[4]	4371	1			T15	34		T16	29		T18	29
values[5]	4013	1			T2	24		T11	61		T16	39
values[6]	4703	1			T2	113		T16	61		T18	20
values[7]	4339	1			T2	62		T13	2		T16	156

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	193	1			T154	10		T122	14		T151	10
auto[0]	values[0]	values[1]	375	1			T30	9		T32	19		T159	16
auto[0]	values[0]	values[2]	182	1			T16	14		T32	8		T51	24
auto[0]	values[0]	values[3]	318	1			T18	17		T191	6		T29	12
auto[0]	values[0]	values[4]	416	1			T29	15		T30	5		T271	22
auto[0]	values[0]	values[5]	201	1			T192	16		T134	12		T272	2
auto[0]	values[0]	values[6]	409	1			T27	13		T29	9		T154	12
auto[0]	values[0]	values[7]	276	1			T2	13		T184	2		T27	13
auto[0]	values[1]	values[0]	503	1			T16	14		T154	15		T159	19
auto[0]	values[1]	values[1]	319	1			T18	11		T84	22		T30	10
auto[0]	values[1]	values[2]	266	1			T260	10		T273	22		T237	20
auto[0]	values[1]	values[3]	484	1			T177	6		T31	29		T32	49
auto[0]	values[1]	values[4]	391	1			T189	24		T155	15		T32	9
auto[0]	values[1]	values[5]	436	1			T27	13		T29	11		T155	12
auto[0]	values[1]	values[6]	303	1			T31	11		T154	15		T51	15
auto[0]	values[1]	values[7]	291	1			T157	15		T122	7		T237	14
auto[0]	values[2]	values[0]	419	1			T29	16		T31	11		T171	37
auto[0]	values[2]	values[1]	235	1			T18	10		T199	6		T31	13
auto[0]	values[2]	values[2]	247	1			T30	7		T32	14		T274	6
auto[0]	values[2]	values[3]	400	1			T56	6		T29	13		T154	13
auto[0]	values[2]	values[4]	299	1			T83	28		T51	13		T161	10
auto[0]	values[2]	values[5]	407	1			T11	61		T27	9		T51	13
auto[0]	values[2]	values[6]	343	1			T2	13		T16	17		T155	15
auto[0]	values[2]	values[7]	270	1			T2	10		T16	51		T27	12
auto[0]	values[3]	values[0]	172	1			T14	12		T159	6		T156	13
auto[0]	values[3]	values[1]	257	1			T190	2		T159	26		T51	12
auto[0]	values[3]	values[2]	301	1			T2	12		T16	10		T56	67
auto[0]	values[3]	values[3]	481	1			T180	26		T194	12		T27	11
auto[0]	values[3]	values[4]	304	1			T183	2		T151	18		T135	24
auto[0]	values[3]	values[5]	193	1			T181	16		T155	9		T241	13
auto[0]	values[3]	values[6]	280	1			T2	24		T16	10		T18	12
auto[0]	values[3]	values[7]	480	1			T2	15		T18	52		T26	13
auto[0]	values[4]	values[0]	343	1			T2	12		T29	10		T275	10
auto[0]	values[4]	values[1]	344	1			T16	9		T168	12		T155	9
auto[0]	values[4]	values[2]	218	1			T18	42		T31	9		T154	11
auto[0]	values[4]	values[3]	244	1			T16	9		T187	2		T31	33
auto[0]	values[4]	values[4]	242	1			T27	10		T160	20		T161	10
auto[0]	values[4]	values[5]	339	1			T18	11		T29	10		T160	31
auto[0]	values[4]	values[6]	258	1			T2	16		T32	31		T51	8
auto[0]	values[4]	values[7]	317	1			T29	11		T32	16		T182	16
auto[0]	values[5]	values[0]	432	1			T31	16		T32	16		T156	41
auto[0]	values[5]	values[1]	300	1			T18	12		T155	8		T156	12
auto[0]	values[5]	values[2]	311	1			T2	17		T161	29		T276	12
auto[0]	values[5]	values[3]	458	1			T167	16		T159	7		T161	33
auto[0]	values[5]	values[4]	346	1			T16	14		T18	11		T178	18
auto[0]	values[5]	values[5]	499	1			T16	32		T18	35		T170	4
auto[0]	values[5]	values[6]	388	1			T16	10		T85	26		T32	25
auto[0]	values[5]	values[7]	316	1			T16	8		T29	22		T176	8
auto[0]	values[6]	values[0]	153	1			T2	11		T277	28		T175	14
auto[0]	values[6]	values[1]	271	1			T27	58		T159	91		T278	4
auto[0]	values[6]	values[2]	213	1			T30	24		T279	8		T31	14
auto[0]	values[6]	values[3]	224	1			T16	14		T18	10		T27	18
auto[0]	values[6]	values[4]	390	1			T161	10		T171	16		T225	15
auto[0]	values[6]	values[5]	195	1			T198	2		T51	10		T172	15
auto[0]	values[6]	values[6]	334	1			T155	14		T163	63		T172	15
auto[0]	values[6]	values[7]	328	1			T16	10		T117	8		T93	2
auto[0]	values[7]	values[0]	269	1			T2	10		T18	12		T27	12
auto[0]	values[7]	values[1]	310	1			T4	20		T103	18		T154	15
auto[0]	values[7]	values[2]	249	1			T18	13		T27	10		T155	14
auto[0]	values[7]	values[3]	147	1			T29	10		T158	34		T161	15
auto[0]	values[7]	values[4]	313	1			T29	15		T280	28		T175	8
auto[0]	values[7]	values[5]	273	1			T2	12		T73	22		T193	8
auto[0]	values[7]	values[6]	191	1			T29	10		T155	17		T31	8
auto[0]	values[7]	values[7]	160	1			T13	2		T16	13		T27	11
auto[1]	values[0]	values[0]	179	1			T154	10		T164	12		T122	8
auto[1]	values[0]	values[1]	216	1			T30	11		T32	9		T159	4
auto[1]	values[0]	values[2]	173	1			T16	6		T32	58		T51	4
auto[1]	values[0]	values[3]	184	1			T18	10		T29	15		T154	7
auto[1]	values[0]	values[4]	242	1			T15	34		T29	5		T30	15
auto[1]	values[0]	values[5]	141	1			T28	6		T134	8		T137	13
auto[1]	values[0]	values[6]	280	1			T27	7		T29	13		T154	12
auto[1]	values[0]	values[7]	263	1			T2	7		T27	28		T29	8
auto[1]	values[1]	values[0]	187	1			T16	26		T154	5		T159	21
auto[1]	values[1]	values[1]	210	1			T18	9		T30	10		T208	28
auto[1]	values[1]	values[2]	133	1			T237	9		T219	21		T137	11
auto[1]	values[1]	values[3]	132	1			T31	13		T32	11		T161	15
auto[1]	values[1]	values[4]	222	1			T155	5		T32	18		T175	12
auto[1]	values[1]	values[5]	166	1			T27	7		T29	9		T155	8
auto[1]	values[1]	values[6]	284	1			T31	34		T154	5		T51	9
auto[1]	values[1]	values[7]	214	1			T281	12		T157	69		T122	13
auto[1]	values[2]	values[0]	148	1			T29	7		T31	9		T171	6
auto[1]	values[2]	values[1]	280	1			T18	10		T31	7		T122	11
auto[1]	values[2]	values[2]	170	1			T30	13		T32	9		T219	19
auto[1]	values[2]	values[3]	593	1			T56	25		T29	7		T154	10
auto[1]	values[2]	values[4]	246	1			T51	7		T161	10		T122	6
auto[1]	values[2]	values[5]	93	1			T27	11		T51	8		T175	11
auto[1]	values[2]	values[6]	258	1			T2	7		T16	4		T155	5
auto[1]	values[2]	values[7]	174	1			T2	12		T16	15		T27	8
auto[1]	values[3]	values[0]	66	1			T159	14		T156	7		T202	6
auto[1]	values[3]	values[1]	142	1			T159	14		T51	8		T171	35
auto[1]	values[3]	values[2]	181	1			T2	22		T16	12		T56	13
auto[1]	values[3]	values[3]	254	1			T196	12		T27	9		T159	110
auto[1]	values[3]	values[4]	220	1			T151	7		T135	40		T136	45
auto[1]	values[3]	values[5]	164	1			T155	24		T242	22		T241	7
auto[1]	values[3]	values[6]	204	1			T2	45		T16	10		T18	8
auto[1]	values[3]	values[7]	204	1			T2	5		T18	1		T26	11
auto[1]	values[4]	values[0]	215	1			T2	8		T29	11		T134	9
auto[1]	values[4]	values[1]	171	1			T16	12		T155	11		T154	9
auto[1]	values[4]	values[2]	158	1			T18	5		T31	30		T154	61
auto[1]	values[4]	values[3]	175	1			T16	11		T31	11		T156	20
auto[1]	values[4]	values[4]	107	1			T27	10		T160	7		T161	10
auto[1]	values[4]	values[5]	262	1			T18	9		T29	10		T160	7
auto[1]	values[4]	values[6]	194	1			T2	8		T32	7		T51	18
auto[1]	values[4]	values[7]	192	1			T29	10		T32	4		T282	14
auto[1]	values[5]	values[0]	121	1			T31	5		T32	10		T156	10
auto[1]	values[5]	values[1]	195	1			T18	8		T174	6		T155	12
auto[1]	values[5]	values[2]	210	1			T2	8		T161	5		T171	73
auto[1]	values[5]	values[3]	233	1			T159	51		T161	8		T121	10
auto[1]	values[5]	values[4]	172	1			T16	15		T18	18		T30	33
auto[1]	values[5]	values[5]	312	1			T16	7		T18	10		T27	9
auto[1]	values[5]	values[6]	535	1			T16	10		T32	5		T160	10
auto[1]	values[5]	values[7]	212	1			T16	17		T29	27		T160	58
auto[1]	values[6]	values[0]	168	1			T2	9		T52	10		T175	6
auto[1]	values[6]	values[1]	97	1			T27	37		T159	16		T213	11
auto[1]	values[6]	values[2]	274	1			T30	22		T31	41		T159	24
auto[1]	values[6]	values[3]	287	1			T16	8		T18	10		T27	7
auto[1]	values[6]	values[4]	294	1			T161	22		T171	4		T225	5
auto[1]	values[6]	values[5]	111	1			T51	10		T172	5		T217	23
auto[1]	values[6]	values[6]	155	1			T155	6		T172	5		T202	7
auto[1]	values[6]	values[7]	369	1			T16	11		T27	14		T29	9
auto[1]	values[7]	values[0]	218	1			T2	10		T18	8		T27	10
auto[1]	values[7]	values[1]	112	1			T154	5		T159	11		T160	8
auto[1]	values[7]	values[2]	142	1			T18	11		T27	10		T155	11
auto[1]	values[7]	values[3]	75	1			T29	10		T161	11		T150	7
auto[1]	values[7]	values[4]	167	1			T29	5		T175	12		T151	31
auto[1]	values[7]	values[5]	221	1			T2	12		T160	7		T151	12
auto[1]	values[7]	values[6]	287	1			T29	10		T155	22		T31	22
auto[1]	values[7]	values[7]	273	1			T16	31		T27	20		T157	5