Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	477	1			T2	9		T14	4		T16	1
auto[ReadAddrCrossIntoMailbox]	325	1			T2	3		T16	4		T18	3
auto[ReadAddrCrossOutOfMailbox]	367	1			T2	5		T14	2		T16	2
auto[ReadAddrCrossAllMailbox]	236	1			T2	3		T14	2		T16	2
auto[ReadAddrOutsideMailbox]	3794	1			T2	33		T4	20		T14	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2604

1

T2

22

T4

10

T14

6

auto[1]

2595

1

T2

31

T4

10

T14

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	840	1			T2	13		T4	6		T15	4
read_ops[0x0b]	808	1			T2	9		T4	2		T14	4
read_ops[0x3b]	852	1			T2	8		T4	4		T14	4
read_ops[0x6b]	886	1			T2	8		T4	4		T16	12
read_ops[0xbb]	898	1			T2	8		T4	4		T15	10
read_ops[0xeb]	915	1			T2	7		T14	4		T15	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T178	4		T56	1		T27	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T2	1		T178	4		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T16	1		T27	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T2	2		T159	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T2	1		T27	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T27	1		T155	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T30	1		T51	2		T171	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T26	1		T27	1		T161	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T2	3		T4	3		T15	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	343	1			T2	6		T4	3		T15	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T2	2		T14	2		T16	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T2	1		T14	2		T56	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T154	1		T159	1		T150	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T18	1		T29	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T16	1		T30	2		T51	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T27	1		T29	2		T155	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T30	2		T161	2		T122	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T175	1		T160	1		T171	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T2	2		T4	1		T16	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T2	4		T4	1		T16	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T178	1		T155	1		T31	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T2	1		T178	1		T155	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T29	1		T31	1		T157	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T27	2		T29	1		T122	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T16	1		T18	2		T30	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T2	1		T31	1		T51	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T14	1		T16	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T2	1		T14	1		T56	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T4	2		T14	1		T16	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T2	5		T4	2		T14	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T2	1		T18	1		T170	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T18	1		T170	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T18	1		T155	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T16	2		T56	2		T29	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T30	1		T155	1		T154	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T2	1		T18	2		T30	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T2	2		T27	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T29	1		T51	1		T156	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T2	1		T4	2		T16	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T2	3		T4	2		T16	6
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T2	3		T18	1		T56	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T155	1		T187	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T30	1		T160	1		T122	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T16	1		T56	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T2	1		T18	1		T29	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T56	1		T159	1		T160	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T27	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T29	1		T31	1		T175	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T4	2		T15	5		T16	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T2	4		T4	2		T15	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T170	1		T29	2		T31	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T170	1		T29	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T2	1		T18	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T27	1		T155	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T2	1		T14	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T14	1		T27	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T29	1		T30	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T16	1		T18	1		T159	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T2	4		T14	1		T15	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	343	1			T2	1		T14	1		T15	2