Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7419162	1			T1	1		T2	128373		T3	1
all_pins[1]	7419162	1			T1	1		T2	128373		T3	1
all_pins[2]	7419162	1			T1	1		T2	128373		T3	1
all_pins[3]	7419162	1			T1	1		T2	128373		T3	1
all_pins[4]	7419162	1			T1	1		T2	128373		T3	1
all_pins[5]	7419162	1			T1	1		T2	128373		T3	1
all_pins[6]	7419162	1			T1	1		T2	128373		T3	1
all_pins[7]	7419162	1			T1	1		T2	128373		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	59278517	1			T1	8		T2	102694		T3	8
values[0x1]	74779	1			T2	40		T36	23		T27	3
transitions[0x0=>0x1]	73380	1			T2	31		T36	15		T27	3
transitions[0x1=>0x0]	73395	1			T2	31		T36	15		T27	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7417092	1			T1	1		T2	128369		T3	1
all_pins[0]	values[0x1]	2070	1			T2	4		T36	3		T37	2
all_pins[0]	transitions[0x0=>0x1]	1335	1			T2	3		T37	1		T50	6
all_pins[0]	transitions[0x1=>0x0]	201	1			T2	4		T36	1		T37	1
all_pins[1]	values[0x0]	7418226	1			T1	1		T2	128368		T3	1
all_pins[1]	values[0x1]	936	1			T2	5		T36	4		T37	2
all_pins[1]	transitions[0x0=>0x1]	602	1			T2	4		T36	4		T37	1
all_pins[1]	transitions[0x1=>0x0]	135	1			T2	2		T36	1		T37	1
all_pins[2]	values[0x0]	7418693	1			T1	1		T2	128370		T3	1
all_pins[2]	values[0x1]	469	1			T2	3		T36	1		T37	2
all_pins[2]	transitions[0x0=>0x1]	419	1			T2	3		T37	2		T154	5
all_pins[2]	transitions[0x1=>0x0]	189	1			T2	3		T36	5		T27	2
all_pins[3]	values[0x0]	7418923	1			T1	1		T2	128370		T3	1
all_pins[3]	values[0x1]	239	1			T2	3		T36	6		T27	2
all_pins[3]	transitions[0x0=>0x1]	169	1			T2	1		T36	4		T27	2
all_pins[3]	transitions[0x1=>0x0]	146	1			T2	8		T36	1		T37	2
all_pins[4]	values[0x0]	7418946	1			T1	1		T2	128363		T3	1
all_pins[4]	values[0x1]	216	1			T2	10		T36	3		T37	2
all_pins[4]	transitions[0x0=>0x1]	170	1			T2	9		T36	1		T37	2
all_pins[4]	transitions[0x1=>0x0]	1835	1			T2	2		T36	1		T27	1
all_pins[5]	values[0x0]	7417281	1			T1	1		T2	128370		T3	1
all_pins[5]	values[0x1]	1881	1			T2	3		T36	3		T27	1
all_pins[5]	transitions[0x0=>0x1]	1839	1			T2	2		T36	3		T27	1
all_pins[5]	transitions[0x1=>0x0]	68714	1			T2	6		T36	2		T154	2
all_pins[6]	values[0x0]	7350406	1			T1	1		T2	128366		T3	1
all_pins[6]	values[0x1]	68756	1			T2	7		T36	2		T37	1
all_pins[6]	transitions[0x0=>0x1]	68702	1			T2	5		T36	2		T154	2
all_pins[6]	transitions[0x1=>0x0]	158	1			T2	3		T36	1		T37	1
all_pins[7]	values[0x0]	7418950	1			T1	1		T2	128368		T3	1
all_pins[7]	values[0x1]	212	1			T2	5		T36	1		T37	2
all_pins[7]	transitions[0x0=>0x1]	144	1			T2	4		T36	1		T37	2
all_pins[7]	transitions[0x1=>0x0]	2017	1			T2	3		T36	3		T37	2