Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4380	1			T2	46		T11	61		T15	34
values[1]	4667	1			T2	45		T16	44		T18	141
values[2]	4106	1			T2	54		T13	2		T16	41
values[3]	4413	1			T2	20		T16	42		T83	28
values[4]	4125	1			T2	40		T4	20		T14	12
values[5]	3969	1			T2	25		T16	25		T18	67
values[6]	3828	1			T2	44		T16	80		T117	8
values[7]	3675	1			T2	44		T16	60		T28	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3298	1			T2	86		T14	12		T16	63
values[1]	4056	1			T2	23		T16	40		T18	47
values[2]	4403	1			T2	24		T16	46		T117	8
values[3]	4317	1			T2	44		T11	61		T15	34
values[4]	4787	1			T2	42		T16	44		T18	89
values[5]	4466	1			T2	45		T16	49		T18	49
values[6]	3803	1			T2	54		T4	20		T13	2
values[7]	4033	1			T16	146		T73	22		T18	47

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32612

1

T2

305

T4

20

T11

61

auto[1]

551

1

T2

13

T16

9

T18

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	388	1			T2	44		T16	20		T30	28
auto[0]	values[0]	values[1]	617	1			T155	20		T156	20		T157	47
auto[0]	values[0]	values[2]	660	1			T26	23		T27	24		T158	34
auto[0]	values[0]	values[3]	643	1			T11	61		T15	34		T18	19
auto[0]	values[0]	values[4]	503	1			T155	30		T154	31		T159	20
auto[0]	values[0]	values[5]	715	1			T160	20		T161	92		T162	10
auto[0]	values[0]	values[6]	314	1			T155	20		T31	44		T151	53
auto[0]	values[0]	values[7]	459	1			T73	22		T27	20		T121	21
auto[0]	values[1]	values[0]	538	1			T27	31		T31	30		T134	27
auto[0]	values[1]	values[1]	545	1			T2	23		T29	20		T30	38
auto[0]	values[1]	values[2]	501	1			T18	20		T163	63		T164	12
auto[0]	values[1]	values[3]	394	1			T32	24		T165	26		T51	24
auto[0]	values[1]	values[4]	875	1			T2	17		T16	42		T18	44
auto[0]	values[1]	values[5]	777	1			T18	27		T29	20		T159	20
auto[0]	values[1]	values[6]	402	1			T136	22		T137	20		T166	20
auto[0]	values[1]	values[7]	559	1			T18	43		T155	20		T167	16
auto[0]	values[2]	values[0]	398	1			T16	20		T155	20		T161	20
auto[0]	values[2]	values[1]	362	1			T168	12		T29	21		T169	6
auto[0]	values[2]	values[2]	501	1			T27	37		T31	20		T154	24
auto[0]	values[2]	values[3]	512	1			T16	21		T27	20		T32	30
auto[0]	values[2]	values[4]	474	1			T2	20		T18	23		T170	4
auto[0]	values[2]	values[5]	518	1			T171	132		T172	19		T135	45
auto[0]	values[2]	values[6]	709	1			T2	34		T13	2		T27	64
auto[0]	values[2]	values[7]	570	1			T85	26		T52	8		T173	4
auto[0]	values[3]	values[0]	424	1			T83	28		T93	2		T174	6
auto[0]	values[3]	values[1]	355	1			T16	18		T155	20		T175	28
auto[0]	values[3]	values[2]	882	1			T30	18		T155	20		T176	8
auto[0]	values[3]	values[3]	547	1			T27	20		T177	6		T31	20
auto[0]	values[3]	values[4]	599	1			T178	18		T27	53		T175	54
auto[0]	values[3]	values[5]	538	1			T2	20		T155	33		T179	34
auto[0]	values[3]	values[6]	566	1			T180	26		T27	19		T29	20
auto[0]	values[3]	values[7]	449	1			T16	22		T56	31		T49	2
auto[0]	values[4]	values[0]	516	1			T2	18		T14	12		T16	22
auto[0]	values[4]	values[1]	597	1			T18	20		T181	16		T182	16
auto[0]	values[4]	values[2]	476	1			T16	21		T183	2		T157	39
auto[0]	values[4]	values[3]	463	1			T2	20		T154	43		T121	23
auto[0]	values[4]	values[4]	606	1			T29	26		T32	37		T159	20
auto[0]	values[4]	values[5]	513	1			T16	29		T31	42		T160	92
auto[0]	values[4]	values[6]	473	1			T4	20		T56	80		T31	44
auto[0]	values[4]	values[7]	411	1			T16	45		T184	2		T29	42
auto[0]	values[5]	values[0]	373	1			T53	20		T150	24		T135	24
auto[0]	values[5]	values[1]	515	1			T18	27		T27	21		T29	20
auto[0]	values[5]	values[2]	510	1			T16	25		T18	19		T185	14
auto[0]	values[5]	values[3]	357	1			T51	20		T172	20		T186	4
auto[0]	values[5]	values[4]	632	1			T84	22		T27	20		T187	2
auto[0]	values[5]	values[5]	506	1			T2	25		T18	20		T188	22
auto[0]	values[5]	values[6]	407	1			T51	20		T160	23		T135	41
auto[0]	values[5]	values[7]	610	1			T189	24		T27	20		T32	59
auto[0]	values[6]	values[0]	345	1			T29	18		T155	38		T32	23
auto[0]	values[6]	values[1]	362	1			T190	2		T154	20		T175	20
auto[0]	values[6]	values[2]	478	1			T2	24		T117	8		T18	20
auto[0]	values[6]	values[3]	591	1			T16	19		T191	6		T29	29
auto[0]	values[6]	values[4]	508	1			T18	20		T192	16		T193	8
auto[0]	values[6]	values[5]	413	1			T103	18		T194	12		T29	23
auto[0]	values[6]	values[6]	456	1			T2	17		T30	20		T154	71
auto[0]	values[6]	values[7]	590	1			T16	59		T29	20		T160	46
auto[0]	values[7]	values[0]	268	1			T2	20		T31	20		T195	20
auto[0]	values[7]	values[1]	627	1			T16	18		T29	20		T51	20
auto[0]	values[7]	values[2]	320	1			T196	12		T155	20		T156	28
auto[0]	values[7]	values[3]	752	1			T2	23		T28	2		T197	28
auto[0]	values[7]	values[4]	495	1			T154	22		T198	2		T51	26
auto[0]	values[7]	values[5]	406	1			T16	20		T27	39		T155	36
auto[0]	values[7]	values[6]	407	1			T29	17		T159	20		T175	20
auto[0]	values[7]	values[7]	335	1			T16	20		T199	6		T51	42
auto[1]	values[0]	values[0]	8	1			T2	2		T16	1		T161	2
auto[1]	values[0]	values[1]	10	1			T157	2		T151	2		T64	2
auto[1]	values[0]	values[2]	18	1			T26	1		T27	1		T157	1
auto[1]	values[0]	values[3]	13	1			T18	1		T27	1		T154	1
auto[1]	values[0]	values[4]	4	1			T155	1		T200	1		T201	1
auto[1]	values[0]	values[5]	19	1			T161	7		T202	2		T166	2
auto[1]	values[0]	values[7]	9	1			T121	3		T203	1		T204	1
auto[1]	values[1]	values[0]	5	1			T205	1		T206	1		T207	2
auto[1]	values[1]	values[1]	9	1			T30	2		T208	2		T209	2
auto[1]	values[1]	values[2]	4	1			T210	2		T211	1		T212	1
auto[1]	values[1]	values[3]	7	1			T32	4		T213	1		T214	2
auto[1]	values[1]	values[4]	24	1			T2	5		T16	2		T18	1
auto[1]	values[1]	values[5]	7	1			T18	2		T64	1		T201	1
auto[1]	values[1]	values[6]	9	1			T136	2		T166	2		T206	1
auto[1]	values[1]	values[7]	11	1			T18	4		T137	1		T202	4
auto[1]	values[2]	values[0]	8	1			T215	1		T216	3		T213	1
auto[1]	values[2]	values[1]	5	1			T154	1		T51	2		T203	1
auto[1]	values[2]	values[2]	8	1			T217	4		T213	2		T218	2
auto[1]	values[2]	values[3]	7	1			T171	1		T138	1		T66	2
auto[1]	values[2]	values[4]	9	1			T18	1		T137	2		T217	2
auto[1]	values[2]	values[5]	9	1			T171	2		T172	1		T135	3
auto[1]	values[2]	values[6]	10	1			T155	1		T160	1		T134	4
auto[1]	values[2]	values[7]	6	1			T52	2		T171	1		T219	1
auto[1]	values[3]	values[0]	3	1			T161	1		T143	2		-	-
auto[1]	values[3]	values[1]	7	1			T16	2		T206	2		T212	2
auto[1]	values[3]	values[2]	6	1			T30	2		T159	1		T203	2
auto[1]	values[3]	values[3]	8	1			T217	1		T66	1		T220	4
auto[1]	values[3]	values[4]	11	1			T160	1		T221	6		T222	1
auto[1]	values[3]	values[5]	5	1			T202	1		T223	1		T222	2
auto[1]	values[3]	values[6]	11	1			T27	1		T175	2		T172	1
auto[1]	values[3]	values[7]	2	1			T122	2		-	-		-	-
auto[1]	values[4]	values[0]	8	1			T2	2		T18	2		T161	1
auto[1]	values[4]	values[1]	16	1			T160	3		T224	2		T210	3
auto[1]	values[4]	values[2]	4	1			T157	1		T225	1		T226	2
auto[1]	values[4]	values[3]	1	1			T172	1		-	-		-	-
auto[1]	values[4]	values[4]	14	1			T29	1		T32	1		T227	1
auto[1]	values[4]	values[5]	15	1			T160	3		T215	3		T203	1
auto[1]	values[4]	values[6]	4	1			T31	1		T122	1		T228	1
auto[1]	values[4]	values[7]	8	1			T202	1		T210	1		T229	5
auto[1]	values[5]	values[1]	13	1			T29	1		T171	2		T230	4
auto[1]	values[5]	values[2]	9	1			T18	1		T157	3		T136	1
auto[1]	values[5]	values[3]	7	1			T202	4		T138	2		T231	1
auto[1]	values[5]	values[4]	12	1			T31	1		T159	2		T136	1
auto[1]	values[5]	values[5]	5	1			T232	2		T233	2		T234	1
auto[1]	values[5]	values[6]	7	1			T160	2		T204	3		T235	2
auto[1]	values[5]	values[7]	6	1			T32	1		T219	2		T202	2
auto[1]	values[6]	values[0]	16	1			T29	2		T155	1		T32	3
auto[1]	values[6]	values[1]	5	1			T135	2		T213	2		T236	1
auto[1]	values[6]	values[2]	16	1			T135	2		T237	1		T238	5
auto[1]	values[6]	values[3]	6	1			T16	2		T157	1		T228	2
auto[1]	values[6]	values[4]	12	1			T171	1		T239	2		T240	4
auto[1]	values[6]	values[5]	11	1			T136	1		T241	1		T219	1
auto[1]	values[6]	values[6]	15	1			T2	3		T154	1		T161	1
auto[1]	values[6]	values[7]	4	1			T202	3		T201	1		-	-
auto[1]	values[7]	values[1]	11	1			T16	2		T203	3		T236	1
auto[1]	values[7]	values[2]	10	1			T171	1		T242	6		T243	3
auto[1]	values[7]	values[3]	9	1			T2	1		T28	4		T62	1
auto[1]	values[7]	values[4]	9	1			T51	2		T135	1		T137	1
auto[1]	values[7]	values[5]	9	1			T27	2		T171	3		T228	3
auto[1]	values[7]	values[6]	13	1			T29	3		T172	1		T205	4
auto[1]	values[7]	values[7]	4	1			T150	1		T135	1		T235	2