Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2591

1

T1

4

T2

4

T5

8

auto[1]

2681

1

T1

6

T2

6

T5

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2649

1

T2

10

T8

10

T10

6

auto[1]

2623

1

T1

10

T5

17

T7

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4290

1

T1

10

T2

9

T5

17

auto[1]

982

1

T2

1

T8

2

T10

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1041	1			T1	1		T2	2		T5	4
valid[1]	1030	1			T1	2		T2	3		T5	3
valid[2]	1057	1			T1	1		T5	6		T7	1
valid[3]	1111	1			T2	4		T5	3		T7	1
valid[4]	1033	1			T1	6		T2	1		T5	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	161	1			T8	3		T16	2		T60	2
auto[0]	auto[0]	valid[0]	auto[1]	269	1			T5	2		T55	1		T26	1
auto[0]	auto[0]	valid[1]	auto[0]	174	1			T8	1		T10	1		T26	1
auto[0]	auto[0]	valid[1]	auto[1]	244	1			T1	1		T5	1		T55	1
auto[0]	auto[0]	valid[2]	auto[0]	163	1			T17	3		T16	1		T60	3
auto[0]	auto[0]	valid[2]	auto[1]	262	1			T1	1		T5	3		T55	1
auto[0]	auto[0]	valid[3]	auto[0]	172	1			T2	3		T10	1		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	272	1			T5	2		T80	2		T298	13
auto[0]	auto[0]	valid[4]	auto[0]	158	1			T2	1		T8	1		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	264	1			T1	2		T80	2		T82	2
auto[0]	auto[1]	valid[0]	auto[0]	176	1			T2	2		T10	1		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	249	1			T1	1		T5	2		T55	2
auto[0]	auto[1]	valid[1]	auto[0]	168	1			T2	2		T10	1		T104	1
auto[0]	auto[1]	valid[1]	auto[1]	254	1			T1	1		T5	2		T55	2
auto[0]	auto[1]	valid[2]	auto[0]	154	1			T8	1		T26	1		T59	1
auto[0]	auto[1]	valid[2]	auto[1]	280	1			T5	3		T7	1		T26	2
auto[0]	auto[1]	valid[3]	auto[0]	193	1			T2	1		T8	1		T10	1
auto[0]	auto[1]	valid[3]	auto[1]	259	1			T5	1		T7	1		T55	4
auto[0]	auto[1]	valid[4]	auto[0]	148	1			T8	1		T26	1		T59	1
auto[0]	auto[1]	valid[4]	auto[1]	270	1			T1	4		T5	1		T59	1
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T92	2		T57	1		T29	2
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T8	1		T25	1		T60	2
auto[1]	auto[0]	valid[2]	auto[0]	93	1			T10	1		T16	1		T59	1
auto[1]	auto[0]	valid[3]	auto[0]	93	1			T59	1		T60	1		T291	1
auto[1]	auto[0]	valid[4]	auto[0]	98	1			T16	1		T299	1		T291	2
auto[1]	auto[1]	valid[0]	auto[0]	103	1			T59	2		T60	2		T104	1
auto[1]	auto[1]	valid[1]	auto[0]	105	1			T2	1		T16	1		T25	1
auto[1]	auto[1]	valid[2]	auto[0]	105	1			T16	1		T26	2		T60	1
auto[1]	auto[1]	valid[3]	auto[0]	122	1			T16	1		T59	2		T60	3
auto[1]	auto[1]	valid[4]	auto[0]	95	1			T8	1		T16	1		T25	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal