Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65743

1

T2

191

T8

165

T9

18

auto[1]

27058

1

T1

10

T5

17

T7

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68963

1

T1

10

T2

125

T5

17

auto[1]

23838

1

T2

66

T8

55

T9

9

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47779	1			T1	10		T2	94		T5	17
others[1]	7695	1			T2	18		T8	15		T9	3
others[2]	7899	1			T2	19		T8	13		T9	1
others[3]	8880	1			T2	24		T8	12		T10	8
interest[1]	5249	1			T2	11		T8	9		T10	1
interest[4]	31494	1			T1	10		T2	61		T5	17
interest[64]	15299	1			T2	25		T8	21		T9	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	21433	1			T2	65		T8	65		T9	4
auto[0]	auto[0]	others[1]	3500	1			T2	14		T8	10		T9	2
auto[0]	auto[0]	others[2]	3618	1			T2	10		T8	9		T9	1
auto[0]	auto[0]	others[3]	4009	1			T2	13		T8	10		T10	4
auto[0]	auto[0]	interest[1]	2363	1			T2	8		T8	3		T10	1
auto[0]	auto[0]	interest[4]	13972	1			T2	44		T8	45		T9	3
auto[0]	auto[0]	interest[64]	6982	1			T2	15		T8	13		T9	2
auto[0]	auto[1]	others[0]	13969	1			T1	10		T5	17		T7	2
auto[0]	auto[1]	others[1]	2250	1			T17	2		T55	17		T26	3
auto[0]	auto[1]	others[2]	2297	1			T55	19		T26	6		T59	4
auto[0]	auto[1]	others[3]	2546	1			T17	1		T55	18		T26	7
auto[0]	auto[1]	interest[1]	1574	1			T17	2		T55	10		T26	1
auto[0]	auto[1]	interest[4]	9428	1			T1	10		T5	17		T7	2
auto[0]	auto[1]	interest[64]	4422	1			T17	2		T55	32		T26	8
auto[1]	auto[0]	others[0]	12377	1			T2	29		T8	30		T9	6
auto[1]	auto[0]	others[1]	1945	1			T2	4		T8	5		T9	1
auto[1]	auto[0]	others[2]	1984	1			T2	9		T8	4		T10	3
auto[1]	auto[0]	others[3]	2325	1			T2	11		T8	2		T10	4
auto[1]	auto[0]	interest[1]	1312	1			T2	3		T8	6		T17	3
auto[1]	auto[0]	interest[4]	8094	1			T2	17		T8	22		T9	4
auto[1]	auto[0]	interest[64]	3895	1			T2	10		T8	8		T9	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal