Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	865	1			T2	20		T36	15		T27	4
all_values[1]	865	1			T2	20		T36	15		T27	4
all_values[2]	865	1			T2	20		T36	15		T27	4
all_values[3]	865	1			T2	20		T36	15		T27	4
all_values[4]	865	1			T2	20		T36	15		T27	4
all_values[5]	865	1			T2	20		T36	15		T27	4
all_values[6]	865	1			T2	20		T36	15		T27	4
all_values[7]	865	1			T2	20		T36	15		T27	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3715

1

T2

89

T36

77

T27

15

auto[1]

3205

1

T2

71

T36

43

T27

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2693

1

T2

53

T36

47

T27

20

auto[1]

4227

1

T2

107

T36

73

T27

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3949

1

T2

88

T36

77

T27

23

auto[1]

2971

1

T2

72

T36

43

T27

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T2	2		T36	7		T27	2
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T2	4		T36	2		T37	2
all_values[0]	auto[0]	auto[1]	auto[0]	138	1			T2	2		T36	1		T27	2
all_values[0]	auto[0]	auto[1]	auto[1]	95	1			T2	1		T36	1		T154	1
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T2	5		T36	1		T37	2
all_values[0]	auto[1]	auto[1]	auto[1]	172	1			T2	6		T36	3		T37	2
all_values[1]	auto[0]	auto[0]	auto[0]	167	1			T2	4		T36	2		T27	2
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T2	1		T36	4		T154	1
all_values[1]	auto[0]	auto[1]	auto[0]	125	1			T36	3		T27	2		T37	2
all_values[1]	auto[0]	auto[1]	auto[1]	110	1			T2	3		T36	3		T154	4
all_values[1]	auto[1]	auto[0]	auto[1]	201	1			T2	8		T36	2		T37	1
all_values[1]	auto[1]	auto[1]	auto[1]	174	1			T2	4		T36	1		T37	3
all_values[2]	auto[0]	auto[0]	auto[0]	173	1			T2	8		T36	3		T37	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T2	3		T36	2		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	157	1			T2	2		T36	3		T37	3
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T2	3		T154	2		T50	5
all_values[2]	auto[1]	auto[0]	auto[1]	200	1			T2	3		T36	4		T27	2
all_values[2]	auto[1]	auto[1]	auto[1]	178	1			T2	1		T36	3		T27	1
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T2	3		T36	2		T27	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T2	2		T36	4		T154	2
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T2	5		T36	1		T37	4
all_values[3]	auto[0]	auto[1]	auto[1]	101	1			T2	1		T36	1		T27	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T2	4		T36	3		T37	2
all_values[3]	auto[1]	auto[1]	auto[1]	191	1			T2	5		T36	4		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T2	1		T36	2		T27	2
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T2	3		T36	7		T154	2
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T27	1		T37	5		T154	4
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T2	4		T37	2		T154	2
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T2	10		T36	3		T27	1
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T2	2		T36	3		T37	1
all_values[5]	auto[0]	auto[0]	auto[0]	255	1			T2	8		T36	2		T27	1
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T2	7		T36	8		T27	1
all_values[5]	auto[1]	auto[0]	auto[1]	211	1			T2	2		T36	4		T27	1
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T2	3		T36	1		T27	1
all_values[6]	auto[0]	auto[0]	auto[0]	214	1			T2	2		T36	7		T37	4
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T2	3		T36	1		T50	3
all_values[6]	auto[0]	auto[1]	auto[0]	146	1			T2	1		T36	2		T27	3
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T2	3		T37	2		T154	1
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T2	4		T36	3		T37	1
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T2	7		T36	2		T27	1
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T2	3		T36	3		T37	2
all_values[7]	auto[0]	auto[0]	auto[1]	105	1			T2	2		T36	4		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T2	5		T36	1		T27	2
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T2	2		T36	1		T27	1
all_values[7]	auto[1]	auto[0]	auto[1]	198	1			T2	4		T36	5		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	167	1			T2	4		T36	1		T37	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal