Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7455514	1			T1	1		T2	622		T3	1
all_values[1]	7455514	1			T1	1		T2	622		T3	1
all_values[2]	7455514	1			T1	1		T2	622		T3	1
all_values[3]	7455514	1			T1	1		T2	622		T3	1
all_values[4]	7455514	1			T1	1		T2	622		T3	1
all_values[5]	7455514	1			T1	1		T2	622		T3	1
all_values[6]	7455514	1			T1	1		T2	622		T3	1
all_values[7]	7455514	1			T1	1		T2	622		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58595065

1

T1

8

T2

4976

T3

8

auto[1]

1049047

1

T10

28

T27

320127

T36

21607

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59564787

1

T1

8

T2

4976

T3

8

auto[1]

79325

1

T4

1061

T10

1184

T13

142

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7336877	1			T1	1		T2	622		T3	1
all_values[0]	auto[0]	auto[1]	44720	1			T4	658		T10	790		T13	111
all_values[0]	auto[1]	auto[0]	72950	1			T10	2		T27	1		T36	4059
all_values[0]	auto[1]	auto[1]	967	1			T10	3		T27	1		T36	259
all_values[1]	auto[0]	auto[0]	7395359	1			T1	1		T2	622		T3	1
all_values[1]	auto[0]	auto[1]	22299	1			T4	372		T10	312		T13	29
all_values[1]	auto[1]	auto[0]	37386	1			T10	1		T36	4206		T64	7
all_values[1]	auto[1]	auto[1]	470	1			T10	2		T27	1		T36	114
all_values[2]	auto[0]	auto[0]	7286081	1			T1	1		T2	622		T3	1
all_values[2]	auto[0]	auto[1]	8200	1			T4	31		T10	65		T13	2
all_values[2]	auto[1]	auto[0]	160831	1			T27	79908		T36	2		T64	3
all_values[2]	auto[1]	auto[1]	402	1			T10	2		T27	123		T36	4
all_values[3]	auto[0]	auto[0]	7284154	1			T1	1		T2	622		T3	1
all_values[3]	auto[0]	auto[1]	194	1			T10	1		T36	1		T93	1
all_values[3]	auto[1]	auto[0]	170974	1			T10	2		T27	80031		T36	4311
all_values[3]	auto[1]	auto[1]	192	1			T10	2		T36	4		T64	3
all_values[4]	auto[0]	auto[0]	7224530	1			T1	1		T2	622		T3	1
all_values[4]	auto[0]	auto[1]	211	1			T10	2		T36	2		T64	6
all_values[4]	auto[1]	auto[0]	230563	1			T27	80032		T36	4314		T64	28540
all_values[4]	auto[1]	auto[1]	210	1			T10	1		T36	4		T64	1
all_values[5]	auto[0]	auto[0]	7330993	1			T1	1		T2	622		T3	1
all_values[5]	auto[0]	auto[1]	380	1			T47	6		T27	2		T36	4
all_values[5]	auto[1]	auto[0]	123946	1			T10	4		T36	4315		T64	5
all_values[5]	auto[1]	auto[1]	195	1			T36	2		T64	3		T65	6
all_values[6]	auto[0]	auto[0]	7294028	1			T1	1		T2	622		T3	1
all_values[6]	auto[0]	auto[1]	238	1			T10	1		T36	5		T64	3
all_values[6]	auto[1]	auto[0]	161020	1			T10	1		T27	80028		T36	4
all_values[6]	auto[1]	auto[1]	228	1			T10	3		T27	2		T36	4
all_values[7]	auto[0]	auto[0]	7366606	1			T1	1		T2	622		T3	1
all_values[7]	auto[0]	auto[1]	195	1			T27	2		T36	1		T64	4
all_values[7]	auto[1]	auto[0]	88489	1			T10	5		T36	3		T64	4
all_values[7]	auto[1]	auto[1]	224	1			T36	2		T64	2		T65	1