Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	40070	1			T3	14		T4	201		T10	604
auto[SpiFlashAddrCfg]	8807	1			T4	62		T10	128		T11	8
auto[SpiFlashAddr3b]	10657	1			T2	3		T4	56		T10	161
auto[SpiFlashAddr4b]	8665	1			T2	9		T4	62		T10	121

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39399

1

T2

12

T3

14

T4

213

auto[1]

28800

1

T4

168

T10

476

T11

26

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37034

1

T2

9

T3

8

T4

197

auto[1]

31165

1

T2

3

T3

6

T4

184

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45435	1			T3	14		T4	234		T10	691
values[1]	1319	1			T4	9		T10	22		T13	12
values[2]	1636	1			T4	9		T10	21		T11	2
values[3]	1625	1			T4	11		T10	34		T11	6
values[4]	1732	1			T4	11		T10	21		T12	6
values[5]	1779	1			T2	3		T4	16		T10	35
values[6]	1642	1			T4	14		T10	26		T11	2
values[7]	1658	1			T4	6		T10	26		T13	8
values[8]	11373	1			T2	9		T4	71		T10	138

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36615

1

T3

14

T11

26

T12

28

auto[1]

31584

1

T2

12

T4

381

T10

1014

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

65723

1

T2

12

T3

14

T4

367

write

2476

1

T4

14

T10

41

T13

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

22704

1

T2

6

T4

132

T10

318

valids[0x1]

45495

1

T2

6

T3

14

T4

249

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1868	1			T3	8		T4	13		T10	25
internal_process_ops[0x5a]	1873	1			T4	13		T10	37		T13	11
internal_process_ops[0x05]	24023	1			T4	92		T10	329		T11	6
internal_process_ops[0x35]	1867	1			T4	9		T10	30		T13	6
internal_process_ops[0x15]	1812	1			T3	6		T4	16		T10	22
internal_process_ops[0x03]	1281	1			T2	6		T4	2		T10	10
internal_process_ops[0x0b]	1327	1			T4	7		T10	4		T12	4
internal_process_ops[0x3b]	1284	1			T4	3		T10	10		T11	2
internal_process_ops[0x6b]	1211	1			T2	3		T4	5		T10	6
internal_process_ops[0xbb]	1252	1			T2	3		T4	1		T10	7
internal_process_ops[0xeb]	1324	1			T4	2		T10	8		T12	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66955

1

T2

12

T3

14

T4

373

auto[1]

1244

1

T4

8

T10

19

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65812

1

T2

12

T3

14

T4

358

auto[1]

2387

1

T4

23

T10

39

T13

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13345

1

T3

14

T12

10

T28

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7144

1

T11

6

T14

8

T28

1

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2551

1

T12

4

T15

8

T28

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2092

1

T11

8

T14

4

T19

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3099

1

T12

8

T15

4

T28

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2595

1

T11

12

T14

6

T19

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2444

1

T12

6

T15

4

T28

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2075

1

T14

2

T19

2

T26

31

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T19

2

T26

2

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

65

1

T26

3

T27

1

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

66

1

T27

1

T32

3

T149

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T31

1

T34

1

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T26

5

T27

2

T32

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T31

1

T34

5

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T26

2

T27

1

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T26

5

T31

2

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T27

1

T34

2

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

66

1

T37

1

T20

3

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T27

1

T31

1

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T26

2

T31

4

T32

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T26

1

T31

2

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

68

1

T26

1

T27

5

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

78

1

T26

2

T32

1

T34

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

86

1

T26

1

T31

1

T34

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10878

1

T4

112

T10

350

T13

209

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8100

1

T4

87

T10

239

T13

106

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1826

1

T4

35

T10

53

T13

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1662

1

T4

22

T10

63

T13

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2221

1

T2

3

T4

28

T10

68

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2177

1

T4

26

T10

82

T13

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1808

1

T2

9

T4

28

T10

52

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1706

1

T4

29

T10

66

T13

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

75

1

T10

2

T13

1

T72

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T4

2

T10

1

T72

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T10

6

T74

3

T150

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T10

6

T36

1

T72

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T4

1

T72

2

T74

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T4

3

T10

2

T59

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T10

6

T59

2

T74

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T4

1

T10

4

T13

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T4

1

T10

4

T13

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

82

1

T4

1

T10

5

T13

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

56

1

T10

1

T59

1

T151

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T10

1

T13

1

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

65

1

T4

2

T10

1

T72

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

76

1

T13

2

T72

4

T150

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T4

2

T10

2

T74

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

73

1

T4

1

T59

2

T72

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4739	1			T28	7		T19	5		T26	51
auto[0]	values[0]	valids[0x1]	19017	1			T3	14		T11	8		T12	14
auto[0]	values[1]	valids[0x1]	669	1			T110	2		T19	1		T26	11
auto[0]	values[2]	valids[0x0]	630	1			T11	2		T26	12		T27	1
auto[0]	values[2]	valids[0x1]	323	1			T26	1		T27	2		T31	3
auto[0]	values[3]	valids[0x0]	599	1			T11	6		T26	6		T27	6
auto[0]	values[3]	valids[0x1]	328	1			T19	1		T152	2		T26	2
auto[0]	values[4]	valids[0x0]	612	1			T12	4		T19	2		T26	8
auto[0]	values[4]	valids[0x1]	376	1			T12	2		T14	2		T15	2
auto[0]	values[5]	valids[0x0]	633	1			T14	6		T152	2		T26	10
auto[0]	values[5]	valids[0x1]	367	1			T26	4		T27	3		T31	2
auto[0]	values[6]	valids[0x0]	605	1			T28	2		T152	2		T26	11
auto[0]	values[6]	valids[0x1]	308	1			T11	2		T28	1		T19	2
auto[0]	values[7]	valids[0x0]	588	1			T14	4		T15	2		T28	1
auto[0]	values[7]	valids[0x1]	367	1			T28	1		T19	1		T26	2
auto[0]	values[8]	valids[0x0]	3995	1			T11	8		T12	4		T15	4
auto[0]	values[8]	valids[0x1]	2459	1			T12	4		T14	4		T15	4
auto[1]	values[0]	valids[0x0]	4707	1			T4	64		T10	154		T13	68
auto[1]	values[0]	valids[0x1]	16972	1			T4	170		T10	537		T13	276
auto[1]	values[1]	valids[0x1]	650	1			T4	9		T10	22		T13	12
auto[1]	values[2]	valids[0x0]	390	1			T4	3		T10	14		T13	2
auto[1]	values[2]	valids[0x1]	293	1			T4	6		T10	7		T13	3
auto[1]	values[3]	valids[0x0]	412	1			T4	5		T10	22		T13	3
auto[1]	values[3]	valids[0x1]	286	1			T4	6		T10	12		T13	4
auto[1]	values[4]	valids[0x0]	447	1			T4	5		T10	11		T13	4
auto[1]	values[4]	valids[0x1]	297	1			T4	6		T10	10		T13	5
auto[1]	values[5]	valids[0x0]	477	1			T2	3		T4	9		T10	13
auto[1]	values[5]	valids[0x1]	302	1			T4	7		T10	22		T13	4
auto[1]	values[6]	valids[0x0]	429	1			T4	9		T10	9		T13	1
auto[1]	values[6]	valids[0x1]	300	1			T4	5		T10	17		T59	8
auto[1]	values[7]	valids[0x0]	431	1			T4	3		T10	17		T13	7
auto[1]	values[7]	valids[0x1]	272	1			T4	3		T10	9		T13	1
auto[1]	values[8]	valids[0x0]	3010	1			T2	3		T4	34		T10	78
auto[1]	values[8]	valids[0x1]	1909	1			T2	6		T4	37		T10	60