Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18517

1

T2

13

T3

19

T4

108

auto[1]

24375

1

T4

103

T10

332

T13

217

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15614

1

T2

13

T3

13

T4

94

auto[1]

27278

1

T3

6

T4

117

T10

381

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7176	1			T3	7		T4	76		T10	74
auto[524288:1048575]	5030	1			T3	1		T4	14		T10	122
auto[1048576:1572863]	5089	1			T2	1		T3	4		T4	20
auto[1572864:2097151]	5132	1			T2	1		T3	2		T4	29
auto[2097152:2621439]	5208	1			T3	3		T4	17		T10	49
auto[2621440:3145727]	5132	1			T2	2		T4	12		T10	28
auto[3145728:3670015]	4715	1			T2	9		T3	2		T4	25
auto[3670016:4194303]	5410	1			T4	18		T10	103		T13	6

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42040

1

T2

13

T3

19

T4

211

auto[1]

852

1

T10

10

T13

7

T26

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34672

1

T2

13

T3

19

T4

170

auto[1]

8220

1

T4

41

T10

125

T13

62

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1911	1			T3	4		T4	16		T10	22
auto[0]	auto[0]	auto[0:524287]	auto[1]	801	1			T3	3		T4	10		T10	13
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1346	1			T3	1		T4	7		T10	22
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	505	1			T4	2		T10	6		T13	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1302	1			T2	1		T3	4		T4	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	511	1			T4	3		T10	8		T13	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1178	1			T2	1		T3	1		T4	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	410	1			T3	1		T4	6		T10	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1184	1			T3	2		T4	5		T10	13
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	456	1			T3	1		T4	3		T10	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1338	1			T2	2		T4	2		T10	14
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	473	1			T4	6		T10	4		T13	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1298	1			T2	9		T3	1		T4	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	518	1			T3	1		T4	2		T10	14
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1231	1			T4	6		T10	18		T13	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	498	1			T10	9		T13	3		T19	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	348	1			T4	8		T10	7		T13	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	175	1			T4	3		T10	5		T26	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	309	1			T4	1		T10	9		T13	7
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	134	1			T10	4		T13	2		T26	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	289	1			T4	1		T10	3		T31	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	130	1			T10	3		T26	1		T31	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	292	1			T13	6		T26	1		T27	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	116	1			T4	1		T13	3		T27	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	307	1			T10	2		T13	3		T26	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	144	1			T10	1		T13	2		T26	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	314	1			T4	1		T10	3		T13	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	152	1			T10	1		T31	1		T32	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	266	1			T10	3		T28	1		T26	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	132	1			T10	1		T26	2		T31	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	311	1			T4	2		T10	9		T13	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	138	1			T4	1		T10	5		T28	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	337	1			T4	5		T10	4		T26	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2748	1			T4	14		T10	23		T26	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	212	1			T4	2		T10	7		T13	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1941	1			T4	2		T10	74		T13	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	247	1			T4	2		T10	6		T13	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2053	1			T4	10		T10	20		T13	52
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	207	1			T4	3		T10	2		T19	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2384	1			T4	10		T10	13		T19	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	241	1			T4	1		T10	3		T13	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2316	1			T4	8		T10	24		T13	84
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	228	1			T10	3		T13	3		T26	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2073	1			T10	3		T13	26		T26	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	237	1			T4	2		T10	4		T26	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1913	1			T4	12		T10	35		T26	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	231	1			T4	3		T10	4		T19	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2344	1			T4	6		T10	38		T19	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	76	1			T4	4		T32	1		T34	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	780	1			T4	16		T32	3		T34	19
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	51	1			T13	1		T59	1		T36	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	532	1			T13	10		T59	1		T36	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	56	1			T10	1		T31	2		T38	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	501	1			T10	46		T31	2		T38	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	56	1			T13	1		T38	1		T196	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	489	1			T13	9		T38	2		T196	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T13	1		T26	1		T27	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	517	1			T13	13		T26	1		T27	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	60	1			T4	1		T36	1		T38	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	494	1			T4	2		T36	13		T38	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	41	1			T10	1		T72	1		T150	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	310	1			T10	1		T72	2		T150	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	67	1			T10	4		T26	1		T32	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	590	1			T10	16		T26	1		T32	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14599	1			T2	13		T3	19		T4	90
auto[0]	auto[0]	auto[1]	361	1			T10	7		T13	4		T31	1
auto[0]	auto[1]	auto[0]	3472	1			T4	18		T10	56		T13	26
auto[0]	auto[1]	auto[1]	85	1			T13	1		T34	2		T37	3
auto[1]	auto[0]	auto[0]	19374	1			T4	80		T10	260		T13	180
auto[1]	auto[0]	auto[1]	338	1			T10	3		T13	2		T26	1
auto[1]	auto[1]	auto[0]	4595	1			T4	23		T10	69		T13	35
auto[1]	auto[1]	auto[1]	68	1			T34	1		T59	1		T37	1