Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22074

1

T3

14

T12

28

T15

16

auto[1]

14541

1

T11

26

T14

20

T28

1

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4817	1			T152	14		T33	22		T32	40
values[1]	4996	1			T46	20		T110	10		T26	72
values[2]	4185	1			T15	16		T19	20		T26	49
values[3]	4935	1			T19	26		T26	92		T27	24
values[4]	4441	1			T3	14		T26	41		T31	20
values[5]	4768	1			T28	20		T27	20		T31	62
values[6]	4241	1			T11	26		T14	20		T26	72
values[7]	4232	1			T12	28		T26	20		T27	41

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4742	1			T26	42		T33	22		T31	71
values[1]	4753	1			T28	20		T110	10		T26	42
values[2]	4334	1			T3	14		T26	48		T32	40
values[3]	4075	1			T11	26		T14	20		T15	16
values[4]	4200	1			T19	20		T26	20		T27	20
values[5]	4760	1			T12	28		T46	20		T26	29
values[6]	5484	1			T26	27		T27	21		T31	107
values[7]	4267	1			T19	26		T26	71		T27	29

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	328	1			T33	22		T211	22		T212	10
auto[0]	values[0]	values[1]	313	1			T37	27		T149	29		T213	14
auto[0]	values[0]	values[2]	394	1			T32	6		T38	83		T169	28
auto[0]	values[0]	values[3]	308	1			T152	14		T185	10		T126	12
auto[0]	values[0]	values[4]	334	1			T21	22		T214	14		T181	20
auto[0]	values[0]	values[5]	233	1			T34	25		T37	17		T126	7
auto[0]	values[0]	values[6]	539	1			T34	8		T36	13		T38	9
auto[0]	values[0]	values[7]	341	1			T209	30		T178	15		T145	21
auto[0]	values[1]	values[0]	569	1			T26	15		T43	34		T37	11
auto[0]	values[1]	values[1]	394	1			T110	10		T149	54		T126	11
auto[0]	values[1]	values[2]	474	1			T34	8		T215	32		T20	24
auto[0]	values[1]	values[3]	481	1			T26	10		T20	33		T195	15
auto[0]	values[1]	values[4]	318	1			T20	36		T21	9		T174	10
auto[0]	values[1]	values[5]	189	1			T46	20		T34	9		T195	15
auto[0]	values[1]	values[6]	366	1			T26	10		T36	13		T172	36
auto[0]	values[1]	values[7]	345	1			T31	11		T36	11		T37	8
auto[0]	values[2]	values[0]	322	1			T37	37		T216	2		T217	8
auto[0]	values[2]	values[1]	325	1			T37	13		T38	13		T75	16
auto[0]	values[2]	values[2]	213	1			T164	11		T218	41		T198	9
auto[0]	values[2]	values[3]	244	1			T15	16		T126	53		T175	5
auto[0]	values[2]	values[4]	410	1			T19	13		T186	15		T188	12
auto[0]	values[2]	values[5]	409	1			T26	12		T31	11		T32	6
auto[0]	values[2]	values[6]	479	1			T31	13		T32	13		T195	69
auto[0]	values[2]	values[7]	225	1			T26	9		T34	12		T38	26
auto[0]	values[3]	values[0]	312	1			T31	18		T37	15		T174	15
auto[0]	values[3]	values[1]	325	1			T26	11		T31	20		T219	18
auto[0]	values[3]	values[2]	237	1			T26	25		T44	26		T126	14
auto[0]	values[3]	values[3]	388	1			T31	23		T34	15		T220	18
auto[0]	values[3]	values[4]	197	1			T36	9		T174	8		T186	6
auto[0]	values[3]	values[5]	606	1			T27	18		T126	48		T193	41
auto[0]	values[3]	values[6]	680	1			T32	10		T34	12		T37	16
auto[0]	values[3]	values[7]	179	1			T19	14		T26	14		T20	18
auto[0]	values[4]	values[0]	430	1			T37	13		T195	22		T193	127
auto[0]	values[4]	values[1]	367	1			T34	27		T37	24		T38	16
auto[0]	values[4]	values[2]	465	1			T3	14		T34	12		T37	32
auto[0]	values[4]	values[3]	313	1			T26	12		T34	10		T38	13
auto[0]	values[4]	values[4]	221	1			T26	8		T21	9		T197	21
auto[0]	values[4]	values[5]	332	1			T38	23		T149	43		T221	20
auto[0]	values[4]	values[6]	288	1			T31	7		T32	25		T174	14
auto[0]	values[4]	values[7]	306	1			T34	13		T36	16		T222	10
auto[0]	values[5]	values[0]	459	1			T34	21		T36	10		T149	19
auto[0]	values[5]	values[1]	423	1			T28	19		T27	12		T31	10
auto[0]	values[5]	values[2]	238	1			T37	14		T223	12		T224	4
auto[0]	values[5]	values[3]	164	1			T31	16		T126	11		T188	11
auto[0]	values[5]	values[4]	210	1			T38	41		T225	37		T226	13
auto[0]	values[5]	values[5]	383	1			T197	80		T227	10		T228	4
auto[0]	values[5]	values[6]	377	1			T31	9		T34	48		T20	28
auto[0]	values[5]	values[7]	527	1			T32	12		T126	102		T197	8
auto[0]	values[6]	values[0]	205	1			T31	13		T126	11		T229	16
auto[0]	values[6]	values[1]	341	1			T26	13		T27	14		T32	15
auto[0]	values[6]	values[2]	205	1			T21	12		T181	11		T193	10
auto[0]	values[6]	values[3]	421	1			T26	17		T27	12		T42	10
auto[0]	values[6]	values[4]	277	1			T31	21		T230	14		T175	13
auto[0]	values[6]	values[5]	560	1			T32	19		T36	11		T21	9
auto[0]	values[6]	values[6]	334	1			T27	10		T31	28		T34	11
auto[0]	values[6]	values[7]	237	1			T26	16		T27	11		T32	11
auto[0]	values[7]	values[0]	282	1			T26	16		T32	11		T34	78
auto[0]	values[7]	values[1]	299	1			T36	13		T38	14		T21	11
auto[0]	values[7]	values[2]	179	1			T51	2		T231	6		T175	44
auto[0]	values[7]	values[3]	204	1			T32	14		T21	12		T174	23
auto[0]	values[7]	values[4]	476	1			T27	13		T31	13		T34	14
auto[0]	values[7]	values[5]	422	1			T12	28		T27	5		T36	66
auto[0]	values[7]	values[6]	399	1			T34	40		T195	28		T181	13
auto[0]	values[7]	values[7]	253	1			T36	8		T20	6		T232	14
auto[1]	values[0]	values[0]	291	1			T186	117		T203	6		T145	8
auto[1]	values[0]	values[1]	360	1			T37	15		T149	6		T126	118
auto[1]	values[0]	values[2]	431	1			T32	34		T38	20		T186	10
auto[1]	values[0]	values[3]	142	1			T126	8		T200	9		T145	56
auto[1]	values[0]	values[4]	198	1			T21	7		T233	12		T181	20
auto[1]	values[0]	values[5]	181	1			T34	6		T37	10		T126	13
auto[1]	values[0]	values[6]	282	1			T34	12		T36	7		T38	13
auto[1]	values[0]	values[7]	142	1			T234	8		T178	5		T145	7
auto[1]	values[1]	values[0]	199	1			T26	7		T37	9		T38	7
auto[1]	values[1]	values[1]	218	1			T149	10		T126	20		T186	38
auto[1]	values[1]	values[2]	245	1			T34	12		T20	2		T235	10
auto[1]	values[1]	values[3]	317	1			T26	13		T20	20		T195	5
auto[1]	values[1]	values[4]	322	1			T20	8		T21	11		T174	11
auto[1]	values[1]	values[5]	183	1			T34	11		T35	22		T195	5
auto[1]	values[1]	values[6]	204	1			T26	17		T36	7		T38	8
auto[1]	values[1]	values[7]	172	1			T31	9		T36	13		T37	12
auto[1]	values[2]	values[0]	271	1			T37	11		T39	32		T236	12
auto[1]	values[2]	values[1]	331	1			T37	37		T38	7		T126	22
auto[1]	values[2]	values[2]	126	1			T237	6		T164	9		T218	5
auto[1]	values[2]	values[3]	126	1			T126	11		T175	18		T146	8
auto[1]	values[2]	values[4]	245	1			T19	7		T186	5		T188	37
auto[1]	values[2]	values[5]	170	1			T26	17		T31	11		T32	25
auto[1]	values[2]	values[6]	142	1			T31	7		T32	7		T195	9
auto[1]	values[2]	values[7]	147	1			T26	11		T34	8		T38	7
auto[1]	values[3]	values[0]	241	1			T31	26		T37	5		T174	5
auto[1]	values[3]	values[1]	128	1			T26	9		T31	12		T20	8
auto[1]	values[3]	values[2]	273	1			T26	23		T126	57		T186	63
auto[1]	values[3]	values[3]	241	1			T31	20		T34	34		T149	5
auto[1]	values[3]	values[4]	243	1			T36	21		T174	12		T186	14
auto[1]	values[3]	values[5]	243	1			T27	6		T126	7		T193	7
auto[1]	values[3]	values[6]	403	1			T32	10		T34	8		T37	19
auto[1]	values[3]	values[7]	239	1			T19	12		T26	10		T20	11
auto[1]	values[4]	values[0]	184	1			T37	29		T195	18		T193	4
auto[1]	values[4]	values[1]	258	1			T34	20		T37	16		T38	9
auto[1]	values[4]	values[2]	314	1			T34	46		T37	13		T195	7
auto[1]	values[4]	values[3]	162	1			T26	9		T34	13		T38	7
auto[1]	values[4]	values[4]	186	1			T26	12		T21	12		T197	4
auto[1]	values[4]	values[5]	172	1			T38	10		T149	10		T184	26
auto[1]	values[4]	values[6]	234	1			T31	13		T32	11		T174	6
auto[1]	values[4]	values[7]	209	1			T34	7		T36	48		T195	26
auto[1]	values[5]	values[0]	273	1			T34	6		T36	15		T149	34
auto[1]	values[5]	values[1]	266	1			T28	1		T27	8		T31	11
auto[1]	values[5]	values[2]	342	1			T37	11		T238	26		T239	21
auto[1]	values[5]	values[3]	85	1			T31	5		T126	14		T188	9
auto[1]	values[5]	values[4]	177	1			T38	4		T240	10		T226	16
auto[1]	values[5]	values[5]	217	1			T197	13		T145	5		T241	11
auto[1]	values[5]	values[6]	214	1			T31	11		T34	5		T20	10
auto[1]	values[5]	values[7]	413	1			T32	8		T126	11		T197	13
auto[1]	values[6]	values[0]	184	1			T31	14		T126	16		T180	16
auto[1]	values[6]	values[1]	131	1			T26	9		T27	14		T32	8
auto[1]	values[6]	values[2]	98	1			T21	10		T181	11		T193	10
auto[1]	values[6]	values[3]	238	1			T11	26		T14	20		T26	6
auto[1]	values[6]	values[4]	200	1			T31	10		T175	10		T242	20
auto[1]	values[6]	values[5]	208	1			T32	6		T36	22		T21	12
auto[1]	values[6]	values[6]	313	1			T27	11		T31	19		T34	9
auto[1]	values[6]	values[7]	289	1			T26	11		T27	18		T32	9
auto[1]	values[7]	values[0]	192	1			T26	4		T32	9		T34	5
auto[1]	values[7]	values[1]	274	1			T36	8		T38	6		T21	9
auto[1]	values[7]	values[2]	100	1			T243	32		T175	9		T244	8
auto[1]	values[7]	values[3]	241	1			T32	21		T21	33		T174	8
auto[1]	values[7]	values[4]	186	1			T27	7		T31	7		T34	6
auto[1]	values[7]	values[5]	252	1			T27	16		T36	25		T37	33
auto[1]	values[7]	values[6]	230	1			T34	9		T195	9		T181	7
auto[1]	values[7]	values[7]	243	1			T36	41		T20	14		T244	10