Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	430	1			T28	1		T26	5		T31	12
auto[ReadAddrCrossIntoMailbox]	326	1			T19	2		T26	2		T27	2
auto[ReadAddrCrossOutOfMailbox]	340	1			T28	2		T19	2		T26	3
auto[ReadAddrCrossAllMailbox]	244	1			T28	1		T26	3		T27	1
auto[ReadAddrOutsideMailbox]	4196	1			T11	4		T12	8		T14	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2685

1

T11

2

T12

4

T14

2

auto[1]

2851

1

T11

2

T12

4

T14

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	933	1			T12	4		T28	1		T19	2
read_ops[0x0b]	996	1			T28	1		T110	2		T19	3
read_ops[0x3b]	926	1			T11	2		T28	1		T19	1
read_ops[0x6b]	863	1			T110	2		T19	2		T26	5
read_ops[0xbb]	858	1			T11	2		T19	3		T26	12
read_ops[0xeb]	960	1			T12	4		T14	4		T28	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T31	1		T126	2		T186	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T20	1		T174	1		T195	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T26	1		T27	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T19	1		T31	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T31	1		T34	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T31	1		T220	1		T126	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T31	1		T34	2		T37	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T36	1		T37	1		T149	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T12	2		T28	1		T152	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	376	1			T12	2		T19	1		T152	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T28	1		T26	1		T31	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T31	1		T32	2		T195	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T19	1		T34	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T34	2		T246	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T19	1		T34	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T31	3		T34	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T27	1		T34	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T34	1		T38	1		T226	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	366	1			T110	1		T26	6		T27	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	376	1			T110	1		T19	1		T26	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T26	1		T31	4		T37	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T197	1		T247	1		T248	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T195	1		T249	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T32	1		T34	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T26	1		T31	3		T37	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T31	1		T34	2		T37	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T31	1		T174	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T28	1		T26	1		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	340	1			T11	1		T19	1		T152	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	367	1			T11	1		T152	1		T26	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T32	1		T34	1		T36	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T31	2		T32	1		T213	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T31	2		T32	1		T38	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T31	2		T37	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T26	1		T32	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T31	1		T38	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T20	1		T181	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T32	1		T37	1		T21	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T110	1		T26	2		T31	7
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T110	1		T19	2		T26	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T32	1		T34	2		T195	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T31	3		T38	1		T126	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T34	1		T220	3		T149	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T27	1		T32	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T31	1		T37	2		T20	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T19	1		T27	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T26	1		T20	1		T220	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T36	1		T38	1		T220	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T11	1		T19	2		T26	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T11	1		T26	7		T27	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T26	2		T219	2		T21	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T26	1		T37	1		T219	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T26	1		T31	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T31	2		T37	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T26	1		T32	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T28	2		T31	5		T36	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T26	1		T37	1		T250	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T31	1		T34	2		T36	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	343	1			T12	2		T14	2		T26	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	408	1			T12	2		T14	2		T19	3