Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7455514	1			T1	1		T2	622		T3	1
all_pins[1]	7455514	1			T1	1		T2	622		T3	1
all_pins[2]	7455514	1			T1	1		T2	622		T3	1
all_pins[3]	7455514	1			T1	1		T2	622		T3	1
all_pins[4]	7455514	1			T1	1		T2	622		T3	1
all_pins[5]	7455514	1			T1	1		T2	622		T3	1
all_pins[6]	7455514	1			T1	1		T2	622		T3	1
all_pins[7]	7455514	1			T1	1		T2	622		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	59476441	1			T1	8		T2	4976		T3	8
values[0x1]	167671	1			T10	13		T27	80006		T36	1192
transitions[0x0=>0x1]	165803	1			T10	11		T27	80005		T36	1071
transitions[0x1=>0x0]	165816	1			T10	11		T27	80005		T36	1071

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7454520	1			T1	1		T2	622		T3	1
all_pins[0]	values[0x1]	994	1			T10	3		T27	1		T36	265
all_pins[0]	transitions[0x0=>0x1]	686	1			T10	1		T36	153		T64	166
all_pins[0]	transitions[0x1=>0x0]	170	1			T36	4		T65	4		T21	4
all_pins[1]	values[0x0]	7455036	1			T1	1		T2	622		T3	1
all_pins[1]	values[0x1]	478	1			T10	2		T27	1		T36	116
all_pins[1]	transitions[0x0=>0x1]	425	1			T10	2		T27	1		T36	113
all_pins[1]	transitions[0x1=>0x0]	352	1			T10	2		T27	125		T36	1
all_pins[2]	values[0x0]	7455109	1			T1	1		T2	622		T3	1
all_pins[2]	values[0x1]	405	1			T10	2		T27	125		T36	4
all_pins[2]	transitions[0x0=>0x1]	359	1			T10	2		T27	125		T36	4
all_pins[2]	transitions[0x1=>0x0]	146	1			T10	2		T36	4		T64	3
all_pins[3]	values[0x0]	7455322	1			T1	1		T2	622		T3	1
all_pins[3]	values[0x1]	192	1			T10	2		T36	4		T64	3
all_pins[3]	transitions[0x0=>0x1]	156	1			T10	2		T36	4		T64	3
all_pins[3]	transitions[0x1=>0x0]	174	1			T10	1		T36	4		T64	1
all_pins[4]	values[0x0]	7455304	1			T1	1		T2	622		T3	1
all_pins[4]	values[0x1]	210	1			T10	1		T36	4		T64	1
all_pins[4]	transitions[0x0=>0x1]	163	1			T10	1		T36	2		T65	4
all_pins[4]	transitions[0x1=>0x0]	4400	1			T36	791		T64	2		T65	4
all_pins[5]	values[0x0]	7451067	1			T1	1		T2	622		T3	1
all_pins[5]	values[0x1]	4447	1			T36	793		T64	3		T65	6
all_pins[5]	transitions[0x0=>0x1]	3190	1			T36	792		T64	3		T65	5
all_pins[5]	transitions[0x1=>0x0]	159464	1			T10	3		T27	79879		T36	3
all_pins[6]	values[0x0]	7294793	1			T1	1		T2	622		T3	1
all_pins[6]	values[0x1]	160721	1			T10	3		T27	79879		T36	4
all_pins[6]	transitions[0x0=>0x1]	160663	1			T10	3		T27	79879		T36	2
all_pins[6]	transitions[0x1=>0x0]	166	1			T64	1		T65	1		T21	4
all_pins[7]	values[0x0]	7455290	1			T1	1		T2	622		T3	1
all_pins[7]	values[0x1]	224	1			T36	2		T64	2		T65	1
all_pins[7]	transitions[0x0=>0x1]	161	1			T36	1		T64	1		T21	5
all_pins[7]	transitions[0x1=>0x0]	944	1			T10	3		T27	1		T36	264