Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4168 1 T110 10 T152 14 T26 20
values[1] 4659 1 T3 14 T11 26 T26 22
values[2] 4190 1 T12 28 T14 20 T28 20
values[3] 4600 1 T19 26 T26 20 T33 22
values[4] 5294 1 T31 71 T34 149 T37 70
values[5] 4986 1 T15 16 T19 20 T26 23
values[6] 4625 1 T26 71 T27 57 T32 54
values[7] 4093 1 T46 20 T26 62 T27 21



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4045 1 T26 87 T31 47 T32 23
values[1] 4440 1 T11 26 T12 28 T110 10
values[2] 5002 1 T19 26 T31 52 T32 100
values[3] 4595 1 T14 20 T15 16 T28 20
values[4] 4910 1 T26 78 T33 22 T32 76
values[5] 4441 1 T3 14 T26 20 T27 49
values[6] 4767 1 T26 20 T27 28 T31 80
values[7] 4415 1 T46 20 T19 20 T27 86



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36003 1 T3 14 T11 26 T12 28
auto[1] 612 1 T26 12 T27 6 T31 9



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 345 1 T31 26 T216 2 T21 42
auto[0] values[0] values[1] 404 1 T110 10 T31 20 T186 33
auto[0] values[0] values[2] 608 1 T32 20 T245 45 T38 20
auto[0] values[0] values[3] 750 1 T152 14 T34 19 T172 36
auto[0] values[0] values[4] 530 1 T38 42 T202 24 T193 20
auto[0] values[0] values[5] 353 1 T26 20 T34 17 T20 20
auto[0] values[0] values[6] 502 1 T34 58 T126 36 T192 12
auto[0] values[0] values[7] 605 1 T35 20 T149 64 T199 8
auto[0] values[1] values[0] 503 1 T26 22 T169 28 T246 20
auto[0] values[1] values[1] 844 1 T11 26 T31 21 T211 22
auto[0] values[1] values[2] 575 1 T31 20 T34 47 T36 32
auto[0] values[1] values[3] 552 1 T27 18 T31 43 T186 20
auto[0] values[1] values[4] 784 1 T32 36 T34 23 T36 20
auto[0] values[1] values[5] 544 1 T3 14 T27 20 T37 48
auto[0] values[1] values[6] 548 1 T31 40 T219 18 T195 24
auto[0] values[1] values[7] 228 1 T126 31 T186 17 T164 29
auto[0] values[2] values[0] 357 1 T26 43 T31 20 T37 20
auto[0] values[2] values[1] 696 1 T12 28 T26 51 T43 34
auto[0] values[2] values[2] 691 1 T32 59 T34 20 T38 43
auto[0] values[2] values[3] 487 1 T14 20 T28 20 T124 24
auto[0] values[2] values[4] 411 1 T26 25 T20 38 T21 45
auto[0] values[2] values[5] 444 1 T38 81 T251 12 T178 20
auto[0] values[2] values[6] 342 1 T185 10 T37 19 T21 20
auto[0] values[2] values[7] 689 1 T27 61 T32 20 T36 25
auto[0] values[3] values[0] 534 1 T26 20 T34 27 T36 30
auto[0] values[3] values[1] 570 1 T34 53 T37 20 T149 34
auto[0] values[3] values[2] 651 1 T19 26 T31 29 T32 20
auto[0] values[3] values[3] 355 1 T184 19 T195 19 T186 19
auto[0] values[3] values[4] 378 1 T33 22 T32 36 T37 20
auto[0] values[3] values[5] 718 1 T32 20 T36 44 T37 47
auto[0] values[3] values[6] 692 1 T252 16 T38 33 T174 19
auto[0] values[3] values[7] 609 1 T34 81 T197 61 T193 19
auto[0] values[4] values[0] 437 1 T174 31 T126 52 T195 20
auto[0] values[4] values[1] 488 1 T31 23 T51 2 T197 65
auto[0] values[4] values[2] 796 1 T34 46 T37 25 T253 4
auto[0] values[4] values[3] 549 1 T254 16 T38 68 T174 35
auto[0] values[4] values[4] 682 1 T220 18 T195 177 T255 8
auto[0] values[4] values[5] 820 1 T31 27 T34 49 T256 6
auto[0] values[4] values[6] 927 1 T31 20 T34 50 T37 20
auto[0] values[4] values[7] 522 1 T37 25 T38 32 T144 71
auto[0] values[5] values[0] 618 1 T44 26 T20 23 T195 99
auto[0] values[5] values[1] 486 1 T26 22 T31 28 T20 27
auto[0] values[5] values[2] 448 1 T34 20 T37 43 T213 14
auto[0] values[5] values[3] 807 1 T15 16 T42 10 T20 25
auto[0] values[5] values[4] 674 1 T37 22 T222 10 T21 20
auto[0] values[5] values[5] 493 1 T32 39 T36 20 T237 6
auto[0] values[5] values[6] 591 1 T186 112 T188 25 T257 24
auto[0] values[5] values[7] 787 1 T19 20 T36 20 T20 27
auto[0] values[6] values[0] 664 1 T32 22 T36 69 T37 20
auto[0] values[6] values[1] 435 1 T26 20 T32 31 T126 20
auto[0] values[6] values[2] 438 1 T34 17 T38 27 T258 20
auto[0] values[6] values[3] 678 1 T26 23 T186 108 T188 29
auto[0] values[6] values[4] 801 1 T26 27 T215 32 T38 19
auto[0] values[6] values[5] 613 1 T27 29 T149 20 T184 53
auto[0] values[6] values[6] 407 1 T27 28 T34 20 T38 18
auto[0] values[6] values[7] 510 1 T34 20 T36 20 T37 20
auto[0] values[7] values[0] 506 1 T195 19 T186 20 T197 73
auto[0] values[7] values[1] 431 1 T200 40 T240 8 T178 22
auto[0] values[7] values[2] 726 1 T34 19 T21 20 T259 12
auto[0] values[7] values[3] 359 1 T26 20 T36 29 T37 35
auto[0] values[7] values[4] 557 1 T26 22 T36 19 T195 20
auto[0] values[7] values[5] 374 1 T31 21 T193 39 T175 29
auto[0] values[7] values[6] 680 1 T26 19 T31 20 T37 20
auto[0] values[7] values[7] 400 1 T46 20 T27 21 T31 21
auto[1] values[0] values[0] 10 1 T31 1 T164 1 T191 4
auto[1] values[0] values[1] 4 1 T163 1 T260 2 T261 1
auto[1] values[0] values[2] 3 1 T21 1 T145 1 T241 1
auto[1] values[0] values[3] 7 1 T34 1 T244 3 T262 2
auto[1] values[0] values[4] 14 1 T38 1 T218 1 T263 1
auto[1] values[0] values[5] 17 1 T34 3 T175 3 T264 2
auto[1] values[0] values[6] 11 1 T126 1 T181 1 T178 1
auto[1] values[0] values[7] 5 1 T35 2 T265 3 - -
auto[1] values[1] values[0] 7 1 T145 1 T266 1 T267 2
auto[1] values[1] values[1] 18 1 T31 1 T149 1 T126 1
auto[1] values[1] values[2] 13 1 T36 1 T175 1 T218 2
auto[1] values[1] values[3] 14 1 T27 2 T197 2 T265 5
auto[1] values[1] values[4] 10 1 T32 4 T126 2 T264 1
auto[1] values[1] values[5] 10 1 T37 2 T178 1 T268 1
auto[1] values[1] values[6] 5 1 T195 1 T269 2 T260 1
auto[1] values[1] values[7] 4 1 T126 1 T186 3 - -
auto[1] values[2] values[0] 8 1 T26 2 T186 1 T270 2
auto[1] values[2] values[1] 13 1 T26 3 T218 2 T271 1
auto[1] values[2] values[2] 8 1 T32 1 T38 2 T175 1
auto[1] values[2] values[3] 4 1 T272 2 T273 1 T261 1
auto[1] values[2] values[4] 21 1 T26 4 T203 1 T200 2
auto[1] values[2] values[5] 11 1 T38 1 T241 1 T263 4
auto[1] values[2] values[6] 2 1 T37 1 T146 1 - -
auto[1] values[2] values[7] 6 1 T27 4 T271 2 - -
auto[1] values[3] values[0] 13 1 T218 2 T191 3 T274 1
auto[1] values[3] values[1] 9 1 T149 1 T181 1 T175 2
auto[1] values[3] values[2] 12 1 T31 3 T20 5 T174 1
auto[1] values[3] values[3] 4 1 T184 1 T195 1 T186 1
auto[1] values[3] values[4] 9 1 T200 2 T275 2 T266 2
auto[1] values[3] values[5] 16 1 T37 1 T144 1 T239 2
auto[1] values[3] values[6] 15 1 T174 1 T126 3 T193 1
auto[1] values[3] values[7] 15 1 T34 2 T197 1 T193 1
auto[1] values[4] values[0] 10 1 T126 3 T175 3 T276 2
auto[1] values[4] values[1] 10 1 T31 1 T197 1 T204 1
auto[1] values[4] values[2] 7 1 T34 3 T267 2 T277 1
auto[1] values[4] values[3] 7 1 T38 3 T174 1 T193 2
auto[1] values[4] values[4] 9 1 T195 4 T144 1 T241 1
auto[1] values[4] values[5] 5 1 T178 1 T263 1 T276 2
auto[1] values[4] values[6] 22 1 T34 1 T20 2 T195 1
auto[1] values[4] values[7] 3 1 T38 1 T278 1 T279 1
auto[1] values[5] values[0] 10 1 T195 2 T280 2 T281 1
auto[1] values[5] values[1] 11 1 T26 1 T31 3 T20 2
auto[1] values[5] values[2] 6 1 T37 3 T267 1 T282 2
auto[1] values[5] values[3] 7 1 T20 1 T149 1 T126 1
auto[1] values[5] values[4] 10 1 T21 1 T186 2 T203 3
auto[1] values[5] values[5] 11 1 T32 1 T283 3 T50 2
auto[1] values[5] values[6] 5 1 T162 1 T284 1 T262 3
auto[1] values[5] values[7] 22 1 T20 3 T39 2 T197 1
auto[1] values[6] values[0] 18 1 T32 1 T36 4 T38 3
auto[1] values[6] values[1] 12 1 T26 1 T244 1 T268 1
auto[1] values[6] values[2] 8 1 T34 3 T38 1 T175 3
auto[1] values[6] values[3] 9 1 T188 1 T193 1 T178 1
auto[1] values[6] values[4] 9 1 T38 1 T271 1 T285 1
auto[1] values[6] values[5] 9 1 T184 4 T207 1 T286 1
auto[1] values[6] values[6] 8 1 T38 2 T193 1 T242 2
auto[1] values[6] values[7] 6 1 T203 1 T241 1 T263 1
auto[1] values[7] values[0] 5 1 T195 1 T236 1 T241 1
auto[1] values[7] values[1] 9 1 T240 2 T145 4 T218 2
auto[1] values[7] values[2] 12 1 T34 1 T204 1 T226 1
auto[1] values[7] values[3] 6 1 T149 1 T198 4 T287 1
auto[1] values[7] values[4] 11 1 T36 2 T145 3 T218 1
auto[1] values[7] values[5] 3 1 T145 2 T288 1 - -
auto[1] values[7] values[6] 10 1 T26 1 T197 1 T289 1
auto[1] values[7] values[7] 4 1 T21 1 T195 1 T278 1

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