Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2813

1

T4

10

T6

13

T7

6

auto[1]

2682

1

T4

13

T6

13

T7

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2832

1

T4

19

T7

7

T10

25

auto[1]

2663

1

T4

4

T6

26

T7

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4391

1

T4

12

T6

26

T7

6

auto[1]

1104

1

T4

11

T7

4

T10

12

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1124	1			T4	6		T6	5		T7	1
valid[1]	1084	1			T4	5		T6	9		T7	5
valid[2]	1095	1			T4	5		T6	3		T7	2
valid[3]	1099	1			T4	5		T6	3		T7	1
valid[4]	1093	1			T4	2		T6	6		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	180	1			T4	2		T10	1		T16	4
auto[0]	auto[0]	valid[0]	auto[1]	265	1			T6	2		T7	1		T9	7
auto[0]	auto[0]	valid[1]	auto[0]	176	1			T7	1		T28	2		T30	1
auto[0]	auto[0]	valid[1]	auto[1]	256	1			T6	5		T7	1		T9	3
auto[0]	auto[0]	valid[2]	auto[0]	173	1			T4	1		T16	2		T29	2
auto[0]	auto[0]	valid[2]	auto[1]	279	1			T6	1		T9	4		T10	2
auto[0]	auto[0]	valid[3]	auto[0]	175	1			T4	1		T7	1		T10	1
auto[0]	auto[0]	valid[3]	auto[1]	282	1			T4	1		T6	2		T9	4
auto[0]	auto[0]	valid[4]	auto[0]	198	1			T7	1		T10	2		T16	2
auto[0]	auto[0]	valid[4]	auto[1]	259	1			T6	3		T8	1		T9	1
auto[0]	auto[1]	valid[0]	auto[0]	187	1			T10	2		T16	1		T29	5
auto[0]	auto[1]	valid[0]	auto[1]	275	1			T6	3		T9	6		T10	1
auto[0]	auto[1]	valid[1]	auto[0]	178	1			T4	1		T10	1		T18	3
auto[0]	auto[1]	valid[1]	auto[1]	252	1			T4	2		T6	4		T7	1
auto[0]	auto[1]	valid[2]	auto[0]	155	1			T4	2		T10	3		T16	2
auto[0]	auto[1]	valid[2]	auto[1]	258	1			T6	2		T9	7		T10	3
auto[0]	auto[1]	valid[3]	auto[0]	158	1			T4	1		T10	1		T16	3
auto[0]	auto[1]	valid[3]	auto[1]	263	1			T4	1		T6	1		T9	6
auto[0]	auto[1]	valid[4]	auto[0]	148	1			T10	2		T28	2		T30	1
auto[0]	auto[1]	valid[4]	auto[1]	274	1			T6	3		T8	1		T9	3
auto[1]	auto[0]	valid[0]	auto[0]	109	1			T4	3		T10	3		T28	1
auto[1]	auto[0]	valid[1]	auto[0]	119	1			T16	1		T29	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	114	1			T4	1		T7	1		T10	1
auto[1]	auto[0]	valid[3]	auto[0]	119	1			T16	1		T19	1		T47	1
auto[1]	auto[0]	valid[4]	auto[0]	109	1			T4	1		T16	1		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	108	1			T4	1		T18	1		T28	1
auto[1]	auto[1]	valid[1]	auto[0]	103	1			T4	2		T7	2		T10	2
auto[1]	auto[1]	valid[2]	auto[0]	116	1			T4	1		T7	1		T10	2
auto[1]	auto[1]	valid[3]	auto[0]	102	1			T4	1		T10	1		T16	2
auto[1]	auto[1]	valid[4]	auto[0]	105	1			T4	1		T10	3		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal