Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72902

1

T4

573

T7

318

T10

862

auto[1]

28494

1

T4

81

T6

403

T7

54

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74334

1

T4

425

T6

403

T7

255

auto[1]

27062

1

T4

229

T7

117

T10

359

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	52042	1			T4	332		T6	213		T7	179
others[1]	8521	1			T4	60		T6	31		T7	30
others[2]	8676	1			T4	67		T6	28		T7	35
others[3]	9734	1			T4	57		T6	42		T7	38
interest[1]	5713	1			T4	30		T6	23		T7	25
interest[4]	34240	1			T4	218		T6	133		T7	113
interest[64]	16710	1			T4	108		T6	66		T7	65

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23445	1			T4	179		T7	102		T10	249
auto[0]	auto[0]	others[1]	3954	1			T4	30		T7	17		T10	53
auto[0]	auto[0]	others[2]	3939	1			T4	33		T7	16		T10	36
auto[0]	auto[0]	others[3]	4389	1			T4	27		T7	20		T10	56
auto[0]	auto[0]	interest[1]	2575	1			T4	19		T7	8		T10	28
auto[0]	auto[0]	interest[4]	15278	1			T4	108		T7	62		T10	166
auto[0]	auto[0]	interest[64]	7538	1			T4	56		T7	38		T10	81
auto[0]	auto[1]	others[0]	14849	1			T4	38		T6	213		T7	29
auto[0]	auto[1]	others[1]	2323	1			T4	7		T6	31		T7	4
auto[0]	auto[1]	others[2]	2379	1			T4	7		T6	28		T7	1
auto[0]	auto[1]	others[3]	2698	1			T4	8		T6	42		T7	5
auto[0]	auto[1]	interest[1]	1581	1			T4	2		T6	23		T7	7
auto[0]	auto[1]	interest[4]	9884	1			T4	34		T6	133		T7	15
auto[0]	auto[1]	interest[64]	4664	1			T4	19		T6	66		T7	8
auto[1]	auto[0]	others[0]	13748	1			T4	115		T7	48		T10	186
auto[1]	auto[0]	others[1]	2244	1			T4	23		T7	9		T10	30
auto[1]	auto[0]	others[2]	2358	1			T4	27		T7	18		T10	29
auto[1]	auto[0]	others[3]	2647	1			T4	22		T7	13		T10	32
auto[1]	auto[0]	interest[1]	1557	1			T4	9		T7	10		T10	26
auto[1]	auto[0]	interest[4]	9078	1			T4	76		T7	36		T10	127
auto[1]	auto[0]	interest[64]	4508	1			T4	33		T7	19		T10	56

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal